arm64: dts: rockchip: Add VPU support for RK3568/RK3566

RK356x has Hantro G1 video decoder capable to decode MPEG2/H.264/VP8
video formats.

This patch enables RK356x video decoder in RK356x device-tree
include.

Tested on [1] with FFmpeg v4l2_request code taken from [2]
with MPEG2, H.642 and VP8 samples with results [3].

[1] https://github.com/warpme/minimyth2
[2] https://github.com/LibreELEC/LibreELEC.tv/blob/master/packages/multimedia/ffmpeg/patches/v4l2-request/ffmpeg-001-v4l2-request.patch
[3] https://github.com/warpme/minimyth2/blob/master/video-test-summary.txt

Signed-off-by: Piotr Oniszczuk <piotr.oniszczuk@gmail.com>
Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Link: https://lore.kernel.org/r/20220214212955.1178947-2-piotr.oniszczuk@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index c66b603..3517971 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -592,6 +592,26 @@
                status = "disabled";
        };
 
+       vpu: video-codec@fdea0400 {
+               compatible = "rockchip,rk3568-vpu";
+               reg = <0x0 0xfdea0000 0x0 0x800>;
+               interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+               clock-names = "aclk", "hclk";
+               iommus = <&vdpu_mmu>;
+               power-domains = <&power RK3568_PD_VPU>;
+       };
+
+       vdpu_mmu: iommu@fdea0800 {
+               compatible = "rockchip,rk3568-iommu";
+               reg = <0x0 0xfdea0800 0x0 0x40>;
+               interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+               clock-names = "aclk", "iface";
+               clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+               power-domains = <&power RK3568_PD_VPU>;
+               #iommu-cells = <0>;
+       };
+
        sdmmc2: mmc@fe000000 {
                compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
                reg = <0x0 0xfe000000 0x0 0x4000>;