drm/xe: Standardize power gate registers

Standardize power gate registers

No functional changes

v2: change commit message (Rodrigo)

Signed-off-by: Riana Tauro <riana.tauro@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240524070916.143022-2-riana.tauro@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 9cacdcf..7c173db 100644 (file)
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -316,11 +316,9 @@
 
 #define FORCEWAKE_GT                           XE_REG(0xa188)
 
-#define PG_ENABLE                              XE_REG(0xa210)
-#define   VD2_MFXVDENC_POWERGATE_ENABLE                REG_BIT(8)
-#define   VD2_HCP_POWERGATE_ENABLE             REG_BIT(7)
-#define   VD0_MFXVDENC_POWERGATE_ENABLE                REG_BIT(4)
-#define   VD0_HCP_POWERGATE_ENABLE             REG_BIT(3)
+#define POWERGATE_ENABLE                       XE_REG(0xa210)
+#define   VDN_HCP_POWERGATE_ENABLE(n)          REG_BIT(3 + 2 * (n))
+#define   VDN_MFXVDENC_POWERGATE_ENABLE(n)     REG_BIT(4 + 2 * (n))
 
 #define CTC_MODE                               XE_REG(0xa26c)
 #define   CTC_SHIFT_PARAMETER_MASK             REG_GENMASK(2, 1)

diff --git a/drivers/gpu/drm/xe/xe_gt_idle.c b/drivers/gpu/drm/xe/xe_gt_idle.c
index 749b7f4..6790b56 100644 (file)
--- a/drivers/gpu/drm/xe/xe_gt_idle.c
+++ b/drivers/gpu/drm/xe/xe_gt_idle.c
@@ -202,7 +202,7 @@ void xe_gt_idle_disable_c6(struct xe_gt *gt)
        xe_device_assert_mem_access(gt_to_xe(gt));
        xe_force_wake_assert_held(gt_to_fw(gt), XE_FORCEWAKE_ALL);
 
-       xe_mmio_write32(gt, PG_ENABLE, 0);
+       xe_mmio_write32(gt, POWERGATE_ENABLE, 0);
        xe_mmio_write32(gt, RC_CONTROL, 0);
        xe_mmio_write32(gt, RC_STATE, 0);
 }

diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index 05db53c..64bc595 100644 (file)
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -238,11 +238,11 @@ static const struct xe_rtp_entry_sr gt_was[] = {
        },
        { XE_RTP_NAME("14020316580"),
          XE_RTP_RULES(MEDIA_VERSION(1301)),
-         XE_RTP_ACTIONS(CLR(PG_ENABLE,
-                            VD0_HCP_POWERGATE_ENABLE |
-                            VD0_MFXVDENC_POWERGATE_ENABLE |
-                            VD2_HCP_POWERGATE_ENABLE |
-                            VD2_MFXVDENC_POWERGATE_ENABLE)),
+         XE_RTP_ACTIONS(CLR(POWERGATE_ENABLE,
+                            VDN_HCP_POWERGATE_ENABLE(0) |
+                            VDN_MFXVDENC_POWERGATE_ENABLE(0) |
+                            VDN_HCP_POWERGATE_ENABLE(2) |
+                            VDN_MFXVDENC_POWERGATE_ENABLE(2))),
        },
        { XE_RTP_NAME("14019449301"),
          XE_RTP_RULES(MEDIA_VERSION(1301), ENGINE_CLASS(VIDEO_DECODE)),