interconnect: qcom: osm-l3: Add per-core EPSS L3 support
authorBjorn Andersson <quic_bjorande@quicinc.com>
Fri, 11 Nov 2022 03:25:08 +0000 (19:25 -0800)
committerGeorgi Djakov <djakov@kernel.org>
Mon, 14 Nov 2022 13:05:30 +0000 (15:05 +0200)
The EPSS instance in e.g. SM8350 and SC8280XP has per-core L3 voting
enabled. In this configuration, the "shared" vote is done using the
REG_L3_VOTE register instead of PERF_STATE.

Rename epss_l3 to clarify that it's affecting the PERF_STATE register
and add a new L3_VOTE description. Given platform lineage it's assumed
that the L3_VOTE-based case will be the predominant one, so use this for
a new generic qcom,epss-l3 compatible.

While adding the EPSS generic, also add qcom,osm-l3.

Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Tested-by: Steev Klimaszewski <steev@kali.org>
Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com>
Link: https://lore.kernel.org/r/20221111032515.3460-4-quic_bjorande@quicinc.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>
drivers/interconnect/qcom/osm-l3.c

index 7d68442..469be73 100644 (file)
@@ -34,6 +34,7 @@
 
 /* EPSS Register offsets */
 #define EPSS_LUT_ROW_SIZE              4
+#define EPSS_REG_L3_VOTE               0x90
 #define EPSS_REG_FREQ_LUT              0x100
 #define EPSS_REG_PERF_STATE            0x320
 
@@ -112,7 +113,7 @@ static const struct qcom_osm_l3_desc osm_l3 = {
        .reg_perf_state = OSM_REG_PERF_STATE,
 };
 
-static const struct qcom_osm_l3_desc epss_l3 = {
+static const struct qcom_osm_l3_desc epss_l3_perf_state = {
        .nodes = epss_l3_nodes,
        .num_nodes = ARRAY_SIZE(epss_l3_nodes),
        .lut_row_size = EPSS_LUT_ROW_SIZE,
@@ -120,6 +121,14 @@ static const struct qcom_osm_l3_desc epss_l3 = {
        .reg_perf_state = EPSS_REG_PERF_STATE,
 };
 
+static const struct qcom_osm_l3_desc epss_l3_l3_vote = {
+       .nodes = epss_l3_nodes,
+       .num_nodes = ARRAY_SIZE(epss_l3_nodes),
+       .lut_row_size = EPSS_LUT_ROW_SIZE,
+       .reg_freq_lut = EPSS_REG_FREQ_LUT,
+       .reg_perf_state = EPSS_REG_L3_VOTE,
+};
+
 static int qcom_osm_l3_set(struct icc_node *src, struct icc_node *dst)
 {
        struct qcom_osm_l3_icc_provider *qp;
@@ -285,12 +294,14 @@ err:
 }
 
 static const struct of_device_id osm_l3_of_match[] = {
+       { .compatible = "qcom,epss-l3", .data = &epss_l3_l3_vote },
+       { .compatible = "qcom,osm-l3", .data = &osm_l3 },
        { .compatible = "qcom,sc7180-osm-l3", .data = &osm_l3 },
-       { .compatible = "qcom,sc7280-epss-l3", .data = &epss_l3 },
+       { .compatible = "qcom,sc7280-epss-l3", .data = &epss_l3_perf_state },
        { .compatible = "qcom,sdm845-osm-l3", .data = &osm_l3 },
        { .compatible = "qcom,sm8150-osm-l3", .data = &osm_l3 },
        { .compatible = "qcom,sc8180x-osm-l3", .data = &osm_l3 },
-       { .compatible = "qcom,sm8250-epss-l3", .data = &epss_l3 },
+       { .compatible = "qcom,sm8250-epss-l3", .data = &epss_l3_perf_state },
        { }
 };
 MODULE_DEVICE_TABLE(of, osm_l3_of_match);