spi: sh-msiof: SIFCTR bitfield conversion

Convert MSIOF FIFO Control Register field accesses to use the
FIELD_PREP() bitfield access macro.

This gets rid of explicit shifts and custom field preparation macros.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/0bf4c366381a8999c9755285272897300852bc18.1747401908.git.geert+renesas@glider.be
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c
index 4f582ec..812e64e 100644 (file)
--- a/drivers/spi/spi-sh-msiof.c
+++ b/drivers/spi/spi-sh-msiof.c
@@ -135,30 +135,26 @@ struct sh_msiof_spi_priv {
 #define SICTR_RXRST            BIT(0)          /* Receive Reset */
 
 /* SIFCTR */
-#define SIFCTR_TFWM_MASK       GENMASK(31, 29) /* Transmit FIFO Watermark */
-#define SIFCTR_TFWM_64         (0UL << 29)     /*  Transfer Request when 64 empty stages */
-#define SIFCTR_TFWM_32         (1UL << 29)     /*  Transfer Request when 32 empty stages */
-#define SIFCTR_TFWM_24         (2UL << 29)     /*  Transfer Request when 24 empty stages */
-#define SIFCTR_TFWM_16         (3UL << 29)     /*  Transfer Request when 16 empty stages */
-#define SIFCTR_TFWM_12         (4UL << 29)     /*  Transfer Request when 12 empty stages */
-#define SIFCTR_TFWM_8          (5UL << 29)     /*  Transfer Request when 8 empty stages */
-#define SIFCTR_TFWM_4          (6UL << 29)     /*  Transfer Request when 4 empty stages */
-#define SIFCTR_TFWM_1          (7UL << 29)     /*  Transfer Request when 1 empty stage */
-#define SIFCTR_TFUA_MASK       GENMASK(26, 20) /* Transmit FIFO Usable Area */
-#define SIFCTR_TFUA_SHIFT      20
-#define SIFCTR_TFUA(i)         ((i) << SIFCTR_TFUA_SHIFT)
-#define SIFCTR_RFWM_MASK       GENMASK(15, 13) /* Receive FIFO Watermark */
-#define SIFCTR_RFWM_1          (0 << 13)       /*  Transfer Request when 1 valid stages */
-#define SIFCTR_RFWM_4          (1 << 13)       /*  Transfer Request when 4 valid stages */
-#define SIFCTR_RFWM_8          (2 << 13)       /*  Transfer Request when 8 valid stages */
-#define SIFCTR_RFWM_16         (3 << 13)       /*  Transfer Request when 16 valid stages */
-#define SIFCTR_RFWM_32         (4 << 13)       /*  Transfer Request when 32 valid stages */
-#define SIFCTR_RFWM_64         (5 << 13)       /*  Transfer Request when 64 valid stages */
-#define SIFCTR_RFWM_128                (6 << 13)       /*  Transfer Request when 128 valid stages */
-#define SIFCTR_RFWM_256                (7 << 13)       /*  Transfer Request when 256 valid stages */
-#define SIFCTR_RFUA_MASK       GENMASK(12, 4)  /* Receive FIFO Usable Area (0x40 = full) */
-#define SIFCTR_RFUA_SHIFT      4
-#define SIFCTR_RFUA(i)         ((i) << SIFCTR_RFUA_SHIFT)
+#define SIFCTR_TFWM            GENMASK(31, 29) /* Transmit FIFO Watermark */
+#define SIFCTR_TFWM_64         0U              /*  Transfer Request when 64 empty stages */
+#define SIFCTR_TFWM_32         1U              /*  Transfer Request when 32 empty stages */
+#define SIFCTR_TFWM_24         2U              /*  Transfer Request when 24 empty stages */
+#define SIFCTR_TFWM_16         3U              /*  Transfer Request when 16 empty stages */
+#define SIFCTR_TFWM_12         4U              /*  Transfer Request when 12 empty stages */
+#define SIFCTR_TFWM_8          5U              /*  Transfer Request when 8 empty stages */
+#define SIFCTR_TFWM_4          6U              /*  Transfer Request when 4 empty stages */
+#define SIFCTR_TFWM_1          7U              /*  Transfer Request when 1 empty stage */
+#define SIFCTR_TFUA            GENMASK(26, 20) /* Transmit FIFO Usable Area */
+#define SIFCTR_RFWM            GENMASK(15, 13) /* Receive FIFO Watermark */
+#define SIFCTR_RFWM_1          0U              /*  Transfer Request when 1 valid stages */
+#define SIFCTR_RFWM_4          1U              /*  Transfer Request when 4 valid stages */
+#define SIFCTR_RFWM_8          2U              /*  Transfer Request when 8 valid stages */
+#define SIFCTR_RFWM_16         3U              /*  Transfer Request when 16 valid stages */
+#define SIFCTR_RFWM_32         4U              /*  Transfer Request when 32 valid stages */
+#define SIFCTR_RFWM_64         5U              /*  Transfer Request when 64 valid stages */
+#define SIFCTR_RFWM_128                6U              /*  Transfer Request when 128 valid stages */
+#define SIFCTR_RFWM_256                7U              /*  Transfer Request when 256 valid stages */
+#define SIFCTR_RFUA            GENMASK(12, 4)  /* Receive FIFO Usable Area (0x40 = full) */
 
 /* SISTR */
 #define SISTR_TFEMP            BIT(29) /* Transmit FIFO Empty */
@@ -811,7 +807,9 @@ static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx,
        }
 
        /* 1 stage FIFO watermarks for DMA */
-       sh_msiof_write(p, SIFCTR, SIFCTR_TFWM_1 | SIFCTR_RFWM_1);
+       sh_msiof_write(p, SIFCTR,
+                      FIELD_PREP(SIFCTR_TFWM, SIFCTR_TFWM_1) |
+                      FIELD_PREP(SIFCTR_RFWM, SIFCTR_RFWM_1));
 
        /* setup msiof transfer mode registers (32-bit words) */
        sh_msiof_spi_set_mode_regs(p, tx, rx, 32, len / 4);