drm/amd/display: Enable SubVP on 1080p60 displays

[Description]
- Previously SubVP would never be selected on 1080p60 displays because
  it has too much vactive margin. However, implement a change to allow
  it like how 1440p60 is allowed.
- Add a new struct such that we have a list of allowed modes for
  enabling subvp with vactive margin (currently 1080p60 and 1440p60)
- Also ensure to block drr + vblank cases to prevent unexpected
  enablement of new display configs
- Update SW cursor fallback for these new potential cases as well

Reviewed-by: Samson Tam <samson.tam@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 84d6327..f3a9fdd 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -5316,7 +5316,7 @@ bool check_subvp_sw_cursor_fallback_req(const struct dc *dc, struct dc_stream_st
        if (dc->current_state->stream_count == 1 && stream->timing.v_addressable >= 2880 &&
                        ((stream->timing.pix_clk_100hz * 100) / stream->timing.v_total / stream->timing.h_total) < 120)
                return true;
-       else if (dc->current_state->stream_count > 1 && stream->timing.v_addressable >= 2160 &&
+       else if (dc->current_state->stream_count > 1 && stream->timing.v_addressable >= 1080 &&
                        ((stream->timing.pix_clk_100hz * 100) / stream->timing.v_total / stream->timing.h_total) < 120)
                return true;
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
index ef0a2b0..389ac7a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
@@ -665,6 +665,30 @@ bool dcn32_check_native_scaling_for_res(struct pipe_ctx *pipe, unsigned int widt
        return is_native_scaling;
 }
 
+/**
+ * disallow_subvp_in_active_plus_blank() - Function to determine disallowed subvp + drr/vblank configs
+ *
+ * @pipe: subvp pipe to be used for the subvp + drr/vblank config
+ *
+ * Since subvp is being enabled on more configs (such as 1080p60), we want
+ * to explicitly block any configs that we don't want to enable. We do not
+ * want to enable any 1080p60 (SubVP) + drr / vblank configs since these
+ * are already convered by FPO.
+ *
+ * Return: True if disallowed, false otherwise
+ */
+static bool disallow_subvp_in_active_plus_blank(struct pipe_ctx *pipe)
+{
+       bool disallow = false;
+
+       if (resource_is_pipe_type(pipe, OPP_HEAD) &&
+                       resource_is_pipe_type(pipe, DPP_PIPE)) {
+               if (pipe->stream->timing.v_addressable == 1080 && pipe->stream->timing.h_addressable == 1920)
+                       disallow = true;
+       }
+       return disallow;
+}
+
 /**
  * dcn32_subvp_drr_admissable() - Determine if SubVP + DRR config is admissible
  *
@@ -688,6 +712,7 @@ bool dcn32_subvp_drr_admissable(struct dc *dc, struct dc_state *context)
        bool drr_pipe_found = false;
        bool drr_psr_capable = false;
        uint64_t refresh_rate = 0;
+       bool subvp_disallow = false;
 
        for (i = 0; i < dc->res_pool->pipe_count; i++) {
                struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
@@ -697,6 +722,7 @@ bool dcn32_subvp_drr_admissable(struct dc *dc, struct dc_state *context)
                        if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
                                subvp_count++;
 
+                               subvp_disallow |= disallow_subvp_in_active_plus_blank(pipe);
                                refresh_rate = (pipe->stream->timing.pix_clk_100hz * (uint64_t)100 +
                                        pipe->stream->timing.v_total * pipe->stream->timing.h_total - (uint64_t)1);
                                refresh_rate = div_u64(refresh_rate, pipe->stream->timing.v_total);
@@ -713,7 +739,7 @@ bool dcn32_subvp_drr_admissable(struct dc *dc, struct dc_state *context)
                }
        }
 
-       if (subvp_count == 1 && non_subvp_pipes == 1 && drr_pipe_found && !drr_psr_capable &&
+       if (subvp_count == 1 && !subvp_disallow && non_subvp_pipes == 1 && drr_pipe_found && !drr_psr_capable &&
                ((uint32_t)refresh_rate < 120))
                result = true;
 
@@ -746,6 +772,7 @@ bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context, int
        struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
        bool vblank_psr_capable = false;
        uint64_t refresh_rate = 0;
+       bool subvp_disallow = false;
 
        for (i = 0; i < dc->res_pool->pipe_count; i++) {
                struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
@@ -755,6 +782,7 @@ bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context, int
                        if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
                                subvp_count++;
 
+                               subvp_disallow |= disallow_subvp_in_active_plus_blank(pipe);
                                refresh_rate = (pipe->stream->timing.pix_clk_100hz * (uint64_t)100 +
                                        pipe->stream->timing.v_total * pipe->stream->timing.h_total - (uint64_t)1);
                                refresh_rate = div_u64(refresh_rate, pipe->stream->timing.v_total);
@@ -772,7 +800,7 @@ bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context, int
        }
 
        if (subvp_count == 1 && non_subvp_pipes == 1 && !drr_pipe_found && !vblank_psr_capable &&
-               ((uint32_t)refresh_rate < 120) &&
+               ((uint32_t)refresh_rate < 120) && !subvp_disallow &&
                vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vblank_w_mall_sub_vp)
                result = true;
 

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index 92e2ddc..c4ffb4b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -45,6 +45,14 @@ static const struct subvp_high_refresh_list subvp_high_refresh_list = {
                                {.width = 1920, .height = 1080, }},
 };
 
+static const struct subvp_active_margin_list subvp_active_margin_list = {
+                       .min_refresh = 55,
+                       .max_refresh = 65,
+                       .res = {
+                               {.width = 2560, .height = 1440, },
+                               {.width = 1920, .height = 1080, }},
+};
+
 struct _vcs_dpi_ip_params_st dcn3_2_ip = {
        .gpuvm_enable = 0,
        .gpuvm_max_page_table_levels = 4,
@@ -3295,25 +3303,24 @@ bool dcn32_allow_subvp_with_active_margin(struct pipe_ctx *pipe)
 {
        bool allow = false;
        uint32_t refresh_rate = 0;
+       uint32_t min_refresh = subvp_active_margin_list.min_refresh;
+       uint32_t max_refresh = subvp_active_margin_list.max_refresh;
+       uint32_t i;
 
-       /* Allow subvp on displays that have active margin for 2560x1440@60hz displays
-        * only for now. There must be no scaling as well.
-        *
-        * For now we only enable on 2560x1440@60hz displays to enable 4K60 + 1440p60 configs
-        * for p-state switching.
-        */
-       if (pipe->stream && pipe->plane_state) {
-               refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 +
-                                               pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1)
-                                               / (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total);
-               if (pipe->stream->timing.v_addressable == 1440 &&
-                               pipe->stream->timing.h_addressable == 2560 &&
-                               refresh_rate >= 55 && refresh_rate <= 65 &&
-                               pipe->plane_state->src_rect.height == 1440 &&
-                               pipe->plane_state->src_rect.width == 2560 &&
-                               pipe->plane_state->dst_rect.height == 1440 &&
-                               pipe->plane_state->dst_rect.width == 2560)
+       for (i = 0; i < SUBVP_ACTIVE_MARGIN_LIST_LEN; i++) {
+               uint32_t width = subvp_active_margin_list.res[i].width;
+               uint32_t height = subvp_active_margin_list.res[i].height;
+
+               refresh_rate = (pipe->stream->timing.pix_clk_100hz * (uint64_t)100 +
+                       pipe->stream->timing.v_total * pipe->stream->timing.h_total - (uint64_t)1);
+               refresh_rate = div_u64(refresh_rate, pipe->stream->timing.v_total);
+               refresh_rate = div_u64(refresh_rate, pipe->stream->timing.h_total);
+
+               if (refresh_rate >= min_refresh && refresh_rate <= max_refresh &&
+                               dcn32_check_native_scaling_for_res(pipe, width, height)) {
                        allow = true;
+                       break;
+               }
        }
        return allow;
 }

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
index b931008..b2f20e6 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
@@ -39,6 +39,7 @@
 #define DCN3_2_MBLK_HEIGHT_8BPE 64
 #define DCN3_2_DCFCLK_DS_INIT_KHZ 10000 // Choose 10Mhz for init DCFCLK DS freq
 #define SUBVP_HIGH_REFRESH_LIST_LEN 4
+#define SUBVP_ACTIVE_MARGIN_LIST_LEN 2
 #define DCN3_2_MAX_SUBVP_PIXEL_RATE_MHZ 1800
 #define DCN3_2_VMIN_DISPCLK_HZ 717000000
 
@@ -57,6 +58,15 @@ struct subvp_high_refresh_list {
        } res[SUBVP_HIGH_REFRESH_LIST_LEN];
 };
 
+struct subvp_active_margin_list {
+       int min_refresh;
+       int max_refresh;
+       struct {
+               int width;
+               int height;
+       } res[SUBVP_ACTIVE_MARGIN_LIST_LEN];
+};
+
 struct dcn32_resource_pool {
        struct resource_pool base;
 };