arm64: tegra: Add GPCDMA support for Tegra I2C
authorAkhil R <akhilrajeev@nvidia.com>
Tue, 6 Sep 2022 14:47:15 +0000 (20:17 +0530)
committerThierry Reding <treding@nvidia.com>
Thu, 15 Sep 2022 19:30:38 +0000 (21:30 +0200)
Add dma properties to support GPCDMA for I2C in Tegra 186 and later
chips

Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
arch/arm64/boot/dts/nvidia/tegra186.dtsi
arch/arm64/boot/dts/nvidia/tegra194.dtsi
arch/arm64/boot/dts/nvidia/tegra234.dtsi

index 526272f..6602fe4 100644 (file)
                clock-names = "div-clk";
                resets = <&bpmp TEGRA186_RESET_I2C1>;
                reset-names = "i2c";
+               iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
+               dma-coherent;
+               dmas = <&gpcdma 21>, <&gpcdma 21>;
+               dma-names = "rx", "tx";
                status = "disabled";
        };
 
                clock-names = "div-clk";
                resets = <&bpmp TEGRA186_RESET_I2C3>;
                reset-names = "i2c";
+               iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
+               dma-coherent;
+               dmas = <&gpcdma 23>, <&gpcdma 23>;
+               dma-names = "rx", "tx";
                status = "disabled";
        };
 
                pinctrl-names = "default", "idle";
                pinctrl-0 = <&state_dpaux1_i2c>;
                pinctrl-1 = <&state_dpaux1_off>;
+               iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
+               dma-coherent;
+               dmas = <&gpcdma 26>, <&gpcdma 26>;
+               dma-names = "rx", "tx";
                status = "disabled";
        };
 
                pinctrl-names = "default", "idle";
                pinctrl-0 = <&state_dpaux_i2c>;
                pinctrl-1 = <&state_dpaux_off>;
+               iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
+               dma-coherent;
+               dmas = <&gpcdma 30>, <&gpcdma 30>;
+               dma-names = "rx", "tx";
                status = "disabled";
        };
 
                clock-names = "div-clk";
                resets = <&bpmp TEGRA186_RESET_I2C7>;
                reset-names = "i2c";
+               iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
+               dma-coherent;
+               dmas = <&gpcdma 27>, <&gpcdma 27>;
+               dma-names = "rx", "tx";
                status = "disabled";
        };
 
                clock-names = "div-clk";
                resets = <&bpmp TEGRA186_RESET_I2C9>;
                reset-names = "i2c";
+               iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
+               dma-coherent;
+               dmas = <&gpcdma 31>, <&gpcdma 31>;
+               dma-names = "rx", "tx";
                status = "disabled";
        };
 
                clock-names = "div-clk";
                resets = <&bpmp TEGRA186_RESET_I2C2>;
                reset-names = "i2c";
+               iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
+               dma-coherent;
+               dmas = <&gpcdma 22>, <&gpcdma 22>;
+               dma-names = "rx", "tx";
                status = "disabled";
        };
 
                clock-names = "div-clk";
                resets = <&bpmp TEGRA186_RESET_I2C8>;
                reset-names = "i2c";
+               iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
+               dma-coherent;
+               dmas = <&gpcdma 0>, <&gpcdma 0>;
+               dma-names = "rx", "tx";
                status = "disabled";
        };
 
index ed2fd95..41f3a7e 100644 (file)
                        clock-names = "div-clk";
                        resets = <&bpmp TEGRA194_RESET_I2C1>;
                        reset-names = "i2c";
+                       iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
+                       dma-coherent;
+                       dmas = <&gpcdma 21>, <&gpcdma 21>;
+                       dma-names = "rx", "tx";
                        status = "disabled";
                };
 
                        clock-names = "div-clk";
                        resets = <&bpmp TEGRA194_RESET_I2C3>;
                        reset-names = "i2c";
+                       iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
+                       dma-coherent;
+                       dmas = <&gpcdma 23>, <&gpcdma 23>;
+                       dma-names = "rx", "tx";
                        status = "disabled";
                };
 
                        pinctrl-0 = <&state_dpaux1_i2c>;
                        pinctrl-1 = <&state_dpaux1_off>;
                        pinctrl-names = "default", "idle";
+                       iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
+                       dma-coherent;
+                       dmas = <&gpcdma 26>, <&gpcdma 26>;
+                       dma-names = "rx", "tx";
                        status = "disabled";
                };
 
                        pinctrl-0 = <&state_dpaux0_i2c>;
                        pinctrl-1 = <&state_dpaux0_off>;
                        pinctrl-names = "default", "idle";
+                       iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
+                       dma-coherent;
+                       dmas = <&gpcdma 30>, <&gpcdma 30>;
+                       dma-names = "rx", "tx";
                        status = "disabled";
                };
 
                        pinctrl-0 = <&state_dpaux2_i2c>;
                        pinctrl-1 = <&state_dpaux2_off>;
                        pinctrl-names = "default", "idle";
+                       iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
+                       dma-coherent;
+                       dmas = <&gpcdma 27>, <&gpcdma 27>;
+                       dma-names = "rx", "tx";
                        status = "disabled";
                };
 
                        pinctrl-0 = <&state_dpaux3_i2c>;
                        pinctrl-1 = <&state_dpaux3_off>;
                        pinctrl-names = "default", "idle";
+                       iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
+                       dma-coherent;
+                       dmas = <&gpcdma 31>, <&gpcdma 31>;
+                       dma-names = "rx", "tx";
                        status = "disabled";
                };
 
                        clock-names = "div-clk";
                        resets = <&bpmp TEGRA194_RESET_I2C2>;
                        reset-names = "i2c";
+                       iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
+                       dma-coherent;
+                       dmas = <&gpcdma 22>, <&gpcdma 22>;
+                       dma-names = "rx", "tx";
                        status = "disabled";
                };
 
                        clock-names = "div-clk";
                        resets = <&bpmp TEGRA194_RESET_I2C8>;
                        reset-names = "i2c";
+                       iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
+                       dma-coherent;
+                       dmas = <&gpcdma 0>, <&gpcdma 0>;
+                       dma-names = "rx", "tx";
                        status = "disabled";
                };
 
index 82903c9..0170bfa 100644 (file)
                        clock-names = "div-clk", "parent";
                        resets = <&bpmp TEGRA234_RESET_I2C1>;
                        reset-names = "i2c";
+                       iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
+                       dma-coherent;
+                       dmas = <&gpcdma 21>, <&gpcdma 21>;
+                       dma-names = "rx", "tx";
                };
 
                cam_i2c: i2c@3180000 {
                        clock-names = "div-clk", "parent";
                        resets = <&bpmp TEGRA234_RESET_I2C3>;
                        reset-names = "i2c";
+                       iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
+                       dma-coherent;
+                       dmas = <&gpcdma 23>, <&gpcdma 23>;
+                       dma-names = "rx", "tx";
                };
 
                dp_aux_ch1_i2c: i2c@3190000 {
                        clock-names = "div-clk", "parent";
                        resets = <&bpmp TEGRA234_RESET_I2C4>;
                        reset-names = "i2c";
+                       iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
+                       dma-coherent;
+                       dmas = <&gpcdma 26>, <&gpcdma 26>;
+                       dma-names = "rx", "tx";
                };
 
                dp_aux_ch0_i2c: i2c@31b0000 {
                        clock-names = "div-clk", "parent";
                        resets = <&bpmp TEGRA234_RESET_I2C6>;
                        reset-names = "i2c";
+                       iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
+                       dma-coherent;
+                       dmas = <&gpcdma 30>, <&gpcdma 30>;
+                       dma-names = "rx", "tx";
                };
 
                dp_aux_ch2_i2c: i2c@31c0000 {
                        clock-names = "div-clk", "parent";
                        resets = <&bpmp TEGRA234_RESET_I2C7>;
                        reset-names = "i2c";
+                       iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
+                       dma-coherent;
+                       dmas = <&gpcdma 27>, <&gpcdma 27>;
+                       dma-names = "rx", "tx";
                };
 
                dp_aux_ch3_i2c: i2c@31e0000 {
                        clock-names = "div-clk", "parent";
                        resets = <&bpmp TEGRA234_RESET_I2C9>;
                        reset-names = "i2c";
+                       iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
+                       dma-coherent;
+                       dmas = <&gpcdma 31>, <&gpcdma 31>;
+                       dma-names = "rx", "tx";
                };
 
                spi@3270000 {
                        assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
                        resets = <&bpmp TEGRA234_RESET_I2C2>;
                        reset-names = "i2c";
+                       iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
+                       dma-coherent;
+                       dmas = <&gpcdma 22>, <&gpcdma 22>;
+                       dma-names = "rx", "tx";
                };
 
                gen8_i2c: i2c@c250000 {
                        assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
                        resets = <&bpmp TEGRA234_RESET_I2C8>;
                        reset-names = "i2c";
+                       iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
+                       dma-coherent;
+                       dmas = <&gpcdma 0>, <&gpcdma 0>;
+                       dma-names = "rx", "tx";
                };
 
                rtc@c2a0000 {