e1000e: Add support for the next LOM generation
authorSasha Neftin <sasha.neftin@intel.com>
Sat, 12 Jun 2021 17:02:20 +0000 (20:02 +0300)
committerTony Nguyen <anthony.l.nguyen@intel.com>
Tue, 20 Jul 2021 23:11:36 +0000 (16:11 -0700)
Add devices IDs for the next LOM generations that will be
available on the next Intel Client platforms
This patch provides the initial support for these devices

Signed-off-by: Sasha Neftin <sasha.neftin@intel.com>
Tested-by: Dvora Fuxbrumer <dvorax.fuxbrumer@linux.intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
drivers/net/ethernet/intel/e1000e/hw.h
drivers/net/ethernet/intel/e1000e/netdev.c

index 36ff936..bcf680e 100644 (file)
@@ -98,10 +98,14 @@ struct e1000_hw;
 #define E1000_DEV_ID_PCH_TGP_I219_V14          0x15FA
 #define E1000_DEV_ID_PCH_TGP_I219_LM15         0x15F4
 #define E1000_DEV_ID_PCH_TGP_I219_V15          0x15F5
+#define E1000_DEV_ID_PCH_RPL_I219_LM23         0x0DC5
+#define E1000_DEV_ID_PCH_RPL_I219_V23          0x0DC6
 #define E1000_DEV_ID_PCH_ADP_I219_LM16         0x1A1E
 #define E1000_DEV_ID_PCH_ADP_I219_V16          0x1A1F
 #define E1000_DEV_ID_PCH_ADP_I219_LM17         0x1A1C
 #define E1000_DEV_ID_PCH_ADP_I219_V17          0x1A1D
+#define E1000_DEV_ID_PCH_RPL_I219_LM22         0x0DC7
+#define E1000_DEV_ID_PCH_RPL_I219_V22          0x0DC8
 #define E1000_DEV_ID_PCH_MTP_I219_LM18         0x550A
 #define E1000_DEV_ID_PCH_MTP_I219_V18          0x550B
 #define E1000_DEV_ID_PCH_MTP_I219_LM19         0x550C
index 59f22a7..152cacb 100644 (file)
@@ -7902,10 +7902,14 @@ static const struct pci_device_id e1000_pci_tbl[] = {
        { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V14), board_pch_cnp },
        { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM15), board_pch_cnp },
        { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V15), board_pch_cnp },
+       { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_LM23), board_pch_cnp },
+       { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_V23), board_pch_cnp },
        { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM16), board_pch_cnp },
        { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V16), board_pch_cnp },
        { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM17), board_pch_cnp },
        { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V17), board_pch_cnp },
+       { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_LM22), board_pch_cnp },
+       { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_V22), board_pch_cnp },
        { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_LM18), board_pch_cnp },
        { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_V18), board_pch_cnp },
        { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_LM19), board_pch_cnp },