if (HAS_LMEMBAR_SMEM_STOLEN(i915)) {
/*
* MTL dsm size is in GGC register.
- * Also MTL uses offset to DSMBASE in ptes, so i915
- * uses dsm_base = 0 to setup stolen region.
+ * Also MTL uses offset to GSMBASE in ptes, so i915
+ * uses dsm_base = 8MBs to setup stolen region, since
+ * DSMBASE = GSMBASE + 8MB.
*/
ret = mtl_get_gms_size(uncore);
if (ret < 0) {
return ERR_PTR(ret);
}
- dsm_base = 0;
+ dsm_base = SZ_8M;
dsm_size = (resource_size_t)(ret * SZ_1M);
GEM_BUG_ON(pci_resource_len(pdev, GEN12_LMEM_BAR) != SZ_256M);
- GEM_BUG_ON((dsm_size + SZ_8M) > lmem_size);
+ GEM_BUG_ON((dsm_base + dsm_size) > lmem_size);
} else {
/* Use DSM base address instead for stolen memory */
dsm_base = intel_uncore_read64(uncore, GEN12_DSMBASE) & GEN12_BDSM_MASK;
dsm_size = ALIGN_DOWN(lmem_size - dsm_base, SZ_1M);
}
- io_size = dsm_size;
- if (HAS_LMEMBAR_SMEM_STOLEN(i915)) {
- io_start = pci_resource_start(pdev, GEN12_LMEM_BAR) + SZ_8M;
- } else if (pci_resource_len(pdev, GEN12_LMEM_BAR) < lmem_size) {
+ if (pci_resource_len(pdev, GEN12_LMEM_BAR) < lmem_size) {
io_start = 0;
io_size = 0;
} else {
io_start = pci_resource_start(pdev, GEN12_LMEM_BAR) + dsm_base;
+ io_size = dsm_size;
}
min_page_size = HAS_64K_PAGES(i915) ? I915_GTT_PAGE_SIZE_64K :