arm64: dts: Update cache properties for socionext
authorPierre Gondois <pierre.gondois@arm.com>
Fri, 20 Oct 2023 19:50:22 +0000 (14:50 -0500)
committerArnd Bergmann <arnd@arndb.de>
Mon, 23 Oct 2023 19:10:34 +0000 (21:10 +0200)
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).

Update the Device Trees accordingly.

Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/20221107155825.1644604-21-pierre.gondois@arm.com
Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20231020195022.4183862-2-robh@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi

index 7bb36b0..54e58d9 100644 (file)
@@ -52,6 +52,7 @@
 
                l2: l2-cache {
                        compatible = "cache";
+                       cache-level = <2>;
                };
        };
 
index 4e21716..18390cb 100644 (file)
 
                a72_l2: l2-cache0 {
                        compatible = "cache";
+                       cache-level = <2>;
                };
 
                a53_l2: l2-cache1 {
                        compatible = "cache";
+                       cache-level = <2>;
                };
        };
 
index 38ccfb4..56e0379 100644 (file)
@@ -83,6 +83,7 @@
 
                l2: l2-cache {
                        compatible = "cache";
+                       cache-level = <2>;
                };
        };