drm/amd/display: Fix DSC enable sequence

[Why]
DSC is enabled before reset link and potentially cause DSC enable fail problem.
[How]
Enable DSC after link is reseted

Signed-off-by: Mike Hsieh <chun-wei.hsieh@amd.com>
Acked-by: Bindu Ramamurthy <bindur12@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 29bc287..ac7a2b7 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3296,7 +3296,8 @@ void core_link_enable_stream(
 
                /* eDP lit up by bios already, no need to enable again. */
                if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
-                                       apply_edp_fast_boot_optimization) {
+                                       apply_edp_fast_boot_optimization &&
+                                       !pipe_ctx->stream->timing.flags.DSC) {
                        pipe_ctx->stream->dpms_off = false;
 #if defined(CONFIG_DRM_AMD_DC_HDCP)
                        update_psp_stream_config(pipe_ctx, false);
@@ -3358,8 +3359,10 @@ void core_link_enable_stream(
                /* Set DPS PPS SDP (AKA "info frames") */
                if (pipe_ctx->stream->timing.flags.DSC) {
                        if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
-                                       dc_is_virtual_signal(pipe_ctx->stream->signal))
+                                       dc_is_virtual_signal(pipe_ctx->stream->signal)) {
+                               dp_set_dsc_on_rx(pipe_ctx, true);
                                dp_set_dsc_pps_sdp(pipe_ctx, true);
+                       }
                }
 
                if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
@@ -3754,7 +3757,8 @@ bool dc_link_should_enable_fec(const struct dc_link *link)
        if ((link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT_MST &&
                        link->local_sink &&
                        link->local_sink->edid_caps.panel_patch.disable_fec) ||
-                       link->connector_signal == SIGNAL_TYPE_EDP) // Disable FEC for eDP
+                       (link->connector_signal == SIGNAL_TYPE_EDP &&
+                                       link->dc->debug.force_enable_edp_fec == false)) // Disable FEC for eDP
                is_fec_disable = true;
 
        if (dc_link_is_fec_supported(link) && !link->dc->debug.disable_fec && !is_fec_disable)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index 48ad1a8..b426f87 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -431,7 +431,7 @@ static void dsc_optc_config_log(struct display_stream_compressor *dsc,
        DC_LOG_DSC("\tslice_width %d", config->slice_width);
 }
 
-static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable)
+bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable)
 {
        struct dc *dc = pipe_ctx->stream->ctx->dc;
        struct dc_stream_state *stream = pipe_ctx->stream;
@@ -541,7 +541,7 @@ bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable)
                goto out;
 
        if (enable) {
-               if (dp_set_dsc_on_rx(pipe_ctx, true)) {
+               {
                        dp_set_dsc_on_stream(pipe_ctx, true);
                        result = true;
                }

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index f9fe03c..d218d66 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -541,6 +541,10 @@ struct dc_debug_options {
        /* Enable dmub aux for legacy ddc */
        bool enable_dmub_aux_for_legacy_ddc;
        bool optimize_edp_link_rate; /* eDP ILR */
+       /* force enable edp FEC */
+       bool force_enable_edp_fec;
+       /* FEC/PSR1 sequence enable delay in 100us */
+       uint8_t fec_enable_delay_in100us;
 };
 
 struct dc_debug_data {

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index 28ff059..5e99553 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -284,6 +284,8 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
        copy_settings_data->debug.u32All = 0;
        copy_settings_data->debug.bitfields.visual_confirm      = dc->dc->debug.visual_confirm == VISUAL_CONFIRM_PSR;
        copy_settings_data->debug.bitfields.use_hw_lock_mgr             = 1;
+       copy_settings_data->fec_enable_status = (link->fec_state == dc_link_fec_enabled);
+       copy_settings_data->fec_enable_delay_in100us = link->dc->debug.fec_enable_delay_in100us;
 
        dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
        dc_dmub_srv_cmd_execute(dc->dmub_srv);

diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
index d390140..9a5ef86 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
@@ -88,5 +88,7 @@ bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable);
 bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable);
 void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable);
 bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx);
+bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable);
+
 
 #endif /* __DC_LINK_DP_H__ */