drm/i915/adl_p: Add initial ADL_P Workarounds

Most of the context WA are already implemented.
Adding adl_p platform tag to reflect so.

v2: adjust comments for clarity (MattR)

BSpec: 54369
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Swathi Dhanavanthri <swathi.dhanavanthri@intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210608174721.17593-1-clinton.a.taylor@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 71ac576..882bfd4 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2667,7 +2667,7 @@ static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
 }
 
 /*
- * Display WA #22010492432: ehl, tgl
+ * Display WA #22010492432: ehl, tgl, adl-p
  * Program half of the nominal DCO divider fraction value.
  */
 static bool
@@ -2675,7 +2675,7 @@ ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
 {
        return ((IS_PLATFORM(i915, INTEL_ELKHARTLAKE) &&
                 IS_JSL_EHL_REVID(i915, EHL_REVID_B0, REVID_FOREVER)) ||
-                IS_TIGERLAKE(i915)) &&
+                IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) &&
                 i915->dpll.ref_clks.nssc == 38400;
 }
 

diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 94e0a56..87b0657 100644 (file)
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -208,7 +208,7 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
                flags |= PIPE_CONTROL_FLUSH_L3;
                flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
                flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
-               /* Wa_1409600907:tgl */
+               /* Wa_1409600907:tgl,adl-p */
                flags |= PIPE_CONTROL_DEPTH_STALL;
                flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
                flags |= PIPE_CONTROL_FLUSH_ENABLE;

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index b62d1e3..977a76e 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -640,15 +640,16 @@ static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine,
        gen12_ctx_gt_tuning_init(engine, wal);
 
        /*
-        * Wa_1409142259:tgl
-        * Wa_1409347922:tgl
-        * Wa_1409252684:tgl
-        * Wa_1409217633:tgl
-        * Wa_1409207793:tgl
-        * Wa_1409178076:tgl
-        * Wa_1408979724:tgl
-        * Wa_14010443199:rkl
-        * Wa_14010698770:rkl
+        * Wa_1409142259:tgl,dg1,adl-p
+        * Wa_1409347922:tgl,dg1,adl-p
+        * Wa_1409252684:tgl,dg1,adl-p
+        * Wa_1409217633:tgl,dg1,adl-p
+        * Wa_1409207793:tgl,dg1,adl-p
+        * Wa_1409178076:tgl,dg1,adl-p
+        * Wa_1408979724:tgl,dg1,adl-p
+        * Wa_14010443199:tgl,rkl,dg1,adl-p
+        * Wa_14010698770:tgl,rkl,dg1,adl-s,adl-p
+        * Wa_1409342910:tgl,rkl,dg1,adl-s,adl-p
         */
        wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3,
                     GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
@@ -1113,7 +1114,7 @@ gen12_gt_workarounds_init(struct drm_i915_private *i915,
 {
        wa_init_mcr(i915, wal);
 
-       /* Wa_14011060649:tgl,rkl,dg1,adls */
+       /* Wa_14011060649:tgl,rkl,dg1,adls,adl-p */
        wa_14011060649(i915, wal);
 }
 
@@ -1633,38 +1634,40 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
                            GEN7_DISABLE_SAMPLER_PREFETCH);
        }
 
-       if (IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
+       if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
            IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
-               /* Wa_1606931601:tgl,rkl,dg1,adl-s */
+               /* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */
                wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
 
                /*
                 * Wa_1407928979:tgl A*
                 * Wa_18011464164:tgl[B0+],dg1[B0+]
                 * Wa_22010931296:tgl[B0+],dg1[B0+]
-                * Wa_14010919138:rkl,dg1,adl-s
+                * Wa_14010919138:rkl,dg1,adl-s,adl-p
                 */
                wa_write_or(wal, GEN7_FF_THREAD_MODE,
                            GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
 
                /*
-                * Wa_1606700617:tgl,dg1
-                * Wa_22010271021:tgl,rkl,dg1, adl-s
+                * Wa_1606700617:tgl,dg1,adl-p
+                * Wa_22010271021:tgl,rkl,dg1,adl-s,adl-p
+                * Wa_14010826681:tgl,dg1,rkl,adl-p
                 */
                wa_masked_en(wal,
                             GEN9_CS_DEBUG_MODE1,
                             FF_DOP_CLOCK_GATE_DISABLE);
        }
 
-       if (IS_ALDERLAKE_S(i915) || IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
+       if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) ||
+           IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
            IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
-               /* Wa_1409804808:tgl,rkl,dg1[a0],adl-s */
+               /* Wa_1409804808:tgl,rkl,dg1[a0],adl-s,adl-p */
                wa_masked_en(wal, GEN7_ROW_CHICKEN2,
                             GEN12_PUSH_CONST_DEREF_HOLD_DIS);
 
                /*
                 * Wa_1409085225:tgl
-                * Wa_14010229206:tgl,rkl,dg1[a0],adl-s
+                * Wa_14010229206:tgl,rkl,dg1[a0],adl-s,adl-p
                 */
                wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
        }

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 45fefa0..ef8d9b2 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7352,15 +7352,17 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
 static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv)
 {
        /* Wa_1409120013:tgl,rkl,adl_s,dg1 */
-       intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN,
-                          ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
+       if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
+           IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv))
+               intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN,
+                                  ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
 
        /* Wa_1409825376:tgl (pre-prod)*/
        if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B1))
                intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |
                           TGL_VRH_GATING_DIS);
 
-       /* Wa_14011059788:tgl,rkl,adl_s,dg1 */
+       /* Wa_14011059788:tgl,rkl,adl_s,dg1,adl-p */
        intel_uncore_rmw(&dev_priv->uncore, GEN10_DFR_RATIO_EN_AND_CHICKEN,
                         0, DFR_DISABLE);