drm/amd/display: Update bounding box values for DCN321

[Why&how]

Update bounding box values as per hardware spec

Fixes: 197485c69543 ("drm/amd/display: Create dcn321_fpu file")
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
index 57b9bd8..342a1bc 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
@@ -106,16 +106,16 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_21_soc = {
        .clock_limits = {
                {
                        .state = 0,
-                       .dcfclk_mhz = 1564.0,
-                       .fabricclk_mhz = 400.0,
-                       .dispclk_mhz = 2150.0,
-                       .dppclk_mhz = 2150.0,
+                       .dcfclk_mhz = 1434.0,
+                       .fabricclk_mhz = 2250.0,
+                       .dispclk_mhz = 1720.0,
+                       .dppclk_mhz = 1720.0,
                        .phyclk_mhz = 810.0,
                        .phyclk_d18_mhz = 667.0,
-                       .phyclk_d32_mhz = 625.0,
+                       .phyclk_d32_mhz = 313.0,
                        .socclk_mhz = 1200.0,
-                       .dscclk_mhz = 716.667,
-                       .dram_speed_mts = 1600.0,
+                       .dscclk_mhz = 573.333,
+                       .dram_speed_mts = 16000.0,
                        .dtbclk_mhz = 1564.0,
                },
        },
@@ -125,14 +125,14 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_21_soc = {
        .sr_exit_z8_time_us = 285.0,
        .sr_enter_plus_exit_z8_time_us = 320,
        .writeback_latency_us = 12.0,
-       .round_trip_ping_latency_dcfclk_cycles = 263,
+       .round_trip_ping_latency_dcfclk_cycles = 207,
        .urgent_latency_pixel_data_only_us = 4,
        .urgent_latency_pixel_mixed_with_vm_data_us = 4,
        .urgent_latency_vm_data_only_us = 4,
-       .fclk_change_latency_us = 20,
-       .usr_retraining_latency_us = 2,
-       .smn_latency_us = 2,
-       .mall_allocated_for_dcn_mbytes = 64,
+       .fclk_change_latency_us = 7,
+       .usr_retraining_latency_us = 0,
+       .smn_latency_us = 0,
+       .mall_allocated_for_dcn_mbytes = 32,
        .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
        .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
        .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,