drm/i915/pci: move intel_pci_config.h under include/drm/intel

Since the PCI registers are used from both i915 display and core, move
intel_pci_config.h to include/drm/intel/pci_config.h. Drop the intel_
prefix from the name to reduce tautology.

With this, we can drop the corresponding xe display compat header.

v2: Rebase

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/5aac6c711c3f0a09fc52f322455a4a4b35f80a82.1775590536.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/i9xx_display_sr.c b/drivers/gpu/drm/i915/display/i9xx_display_sr.c
index 9354194..1eb2f63 100644 (file)
--- a/drivers/gpu/drm/i915/display/i9xx_display_sr.c
+++ b/drivers/gpu/drm/i915/display/i9xx_display_sr.c
@@ -4,13 +4,13 @@
  */
 
 #include <drm/drm_device.h>
+#include <drm/intel/pci_config.h>
 
 #include "i9xx_display_sr.h"
 #include "i9xx_wm_regs.h"
 #include "intel_de.h"
 #include "intel_display_regs.h"
 #include "intel_gmbus.h"
-#include "intel_pci_config.h"
 
 static void i9xx_display_save_swf(struct intel_display *display)
 {

diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c b/drivers/gpu/drm/i915/display/intel_backlight.c
index 34e95f0..b128896 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_backlight.c
@@ -11,6 +11,7 @@
 
 #include <drm/drm_file.h>
 #include <drm/drm_print.h>
+#include <drm/intel/pci_config.h>
 
 #include "intel_backlight.h"
 #include "intel_backlight_regs.h"
@@ -23,7 +24,6 @@
 #include "intel_dp_aux_backlight.h"
 #include "intel_dsi_dcs_backlight.h"
 #include "intel_panel.h"
-#include "intel_pci_config.h"
 #include "intel_pps.h"
 #include "intel_quirks.h"
 

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 82955cf..8feba2e 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -28,6 +28,7 @@
 #include <drm/drm_fixed.h>
 #include <drm/drm_print.h>
 #include <drm/intel/intel_pcode_regs.h>
+#include <drm/intel/pci_config.h>
 
 #include "hsw_ips.h"
 #include "intel_atomic.h"
@@ -43,7 +44,6 @@
 #include "intel_dram.h"
 #include "intel_mchbar.h"
 #include "intel_parent.h"
-#include "intel_pci_config.h"
 #include "intel_plane.h"
 #include "intel_psr.h"
 #include "intel_step.h"

diff --git a/drivers/gpu/drm/i915/display/intel_lpe_audio.c b/drivers/gpu/drm/i915/display/intel_lpe_audio.c
index 117b606..7754933 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_lpe_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_lpe_audio.c
@@ -70,11 +70,11 @@
 
 #include <drm/drm_print.h>
 #include <drm/intel/intel_lpe_audio.h>
+#include <drm/intel/pci_config.h>
 
 #include "intel_audio_regs.h"
 #include "intel_de.h"
 #include "intel_lpe_audio.h"
-#include "intel_pci_config.h"
 
 #define HAS_LPE_AUDIO(display) ((display)->audio.lpe.platdev)
 

diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c
index e25be56..9f88b7c 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_opregion.c
+++ b/drivers/gpu/drm/i915/display/intel_opregion.c
@@ -34,13 +34,13 @@
 #include <drm/drm_edid.h>
 #include <drm/drm_file.h>
 #include <drm/drm_print.h>
+#include <drm/intel/pci_config.h>
 
 #include "intel_acpi.h"
 #include "intel_backlight.h"
 #include "intel_display_core.h"
 #include "intel_display_types.h"
 #include "intel_opregion.h"
-#include "intel_pci_config.h"
 
 #define OPREGION_HEADER_OFFSET 0
 #define OPREGION_ACPI_OFFSET   0x100

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index 5838fb3..1cfdcf5 100644 (file)
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -11,6 +11,7 @@
 #include <drm/intel/display_parent_interface.h>
 #include <drm/intel/i915_drm.h>
 #include <drm/intel/mchbar_regs.h>
+#include <drm/intel/pci_config.h>
 
 #include "gem/i915_gem_lmem.h"
 #include "gem/i915_gem_region.h"
@@ -24,7 +25,6 @@
 #include "i915_reg.h"
 #include "i915_utils.h"
 #include "i915_vgpu.h"
-#include "intel_pci_config.h"
 
 struct intel_stolen_node {
        struct drm_i915_private *i915;

diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 08c4e73..64ca5bb 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -12,6 +12,7 @@
 #include <drm/drm_print.h>
 #include <drm/intel/i915_drm.h>
 #include <drm/intel/intel-gtt.h>
+#include <drm/intel/pci_config.h>
 
 #include "gem/i915_gem_lmem.h"
 
@@ -20,7 +21,6 @@
 #include "intel_gpu_commands.h"
 #include "intel_gt.h"
 #include "intel_gt_regs.h"
-#include "intel_pci_config.h"
 #include "intel_ring.h"
 #include "i915_drv.h"
 #include "i915_pci.h"

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index d76121e..5c7f862 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -6,6 +6,7 @@
 #include <drm/drm_managed.h>
 #include <drm/intel/intel-gtt.h>
 #include <drm/intel/intel_gmd_interrupt_regs.h>
+#include <drm/intel/pci_config.h>
 
 #include "gem/i915_gem_internal.h"
 #include "gem/i915_gem_lmem.h"
@@ -28,7 +29,6 @@
 #include "intel_gt_requests.h"
 #include "intel_migrate.h"
 #include "intel_mocs.h"
-#include "intel_pci_config.h"
 #include "intel_rc6.h"
 #include "intel_renderstate.h"
 #include "intel_rps.h"

diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index a30060f..b8a3956 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -4,12 +4,12 @@
  */
 
 #include <drm/drm_print.h>
+#include <drm/intel/pci_config.h>
 
 #include "i915_drv.h"
 #include "i915_pci.h"
 #include "i915_reg.h"
 #include "intel_memory_region.h"
-#include "intel_pci_config.h"
 #include "intel_region_lmem.h"
 #include "intel_region_ttm.h"
 #include "gem/i915_gem_lmem.h"

diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index 4d0ea95..3727287 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -8,6 +8,7 @@
 #include <linux/string_helpers.h>
 
 #include <drm/intel/mchbar_regs.h>
+#include <drm/intel/pci_config.h>
 
 #include "display/intel_display_reset.h"
 #include "display/intel_overlay.h"
@@ -29,7 +30,6 @@
 #include "intel_gt_pm.h"
 #include "intel_gt_print.h"
 #include "intel_gt_requests.h"
-#include "intel_pci_config.h"
 #include "intel_reset.h"
 
 #define RESET_MAX_RETRIES 3

diff --git a/drivers/gpu/drm/i915/gvt/cfg_space.c b/drivers/gpu/drm/i915/gvt/cfg_space.c
index 1937e04..e00c147 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/cfg_space.c
+++ b/drivers/gpu/drm/i915/gvt/cfg_space.c
@@ -32,10 +32,10 @@
  */
 
 #include <drm/drm_print.h>
+#include <drm/intel/pci_config.h>
 
 #include "gvt.h"
 #include "i915_drv.h"
-#include "intel_pci_config.h"
 
 enum {
        INTEL_GVT_PCI_BAR_GTTMMIO = 0,

diff --git a/drivers/gpu/drm/i915/i915_gmch.c b/drivers/gpu/drm/i915/i915_gmch.c
index 2d55831..b0ef6ef 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gmch.c
+++ b/drivers/gpu/drm/i915/i915_gmch.c
@@ -5,10 +5,10 @@
 
 #include <drm/drm_managed.h>
 #include <drm/drm_print.h>
+#include <drm/intel/pci_config.h>
 
 #include "i915_drv.h"
 #include "i915_gmch.h"
-#include "intel_pci_config.h"
 
 static void i915_gmch_bridge_release(struct drm_device *dev, void *bridge)
 {

diff --git a/drivers/gpu/drm/i915/i915_overlay.c b/drivers/gpu/drm/i915/i915_overlay.c
index c2d712b..2d7aff5 100644 (file)
--- a/drivers/gpu/drm/i915/i915_overlay.c
+++ b/drivers/gpu/drm/i915/i915_overlay.c
@@ -7,6 +7,7 @@
 
 #include <drm/intel/display_parent_interface.h>
 #include <drm/intel/intel_gmd_interrupt_regs.h>
+#include <drm/intel/pci_config.h>
 
 #include "gem/i915_gem_internal.h"
 #include "gem/i915_gem_object_frontbuffer.h"
@@ -18,7 +19,6 @@
 #include "i915_drv.h"
 #include "i915_overlay.h"
 #include "i915_reg.h"
-#include "intel_pci_config.h"
 
 #include "display/intel_frontbuffer.h"
 

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index d966a00..82415af 100644 (file)
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -24,6 +24,7 @@
 
 #include <drm/drm_color_mgmt.h>
 #include <drm/drm_drv.h>
+#include <drm/intel/pci_config.h>
 #include <drm/intel/pciids.h>
 
 #include "display/intel_display_driver.h"
@@ -35,7 +36,6 @@
 #include "i915_drv.h"
 #include "i915_pci.h"
 #include "i915_reg.h"
-#include "intel_pci_config.h"
 
 __diag_push();
 __diag_ignore_all("-Woverride-init", "Allow field initialization overrides for device info");

diff --git a/drivers/gpu/drm/i915/intel_pci_config.h b/drivers/gpu/drm/i915/intel_pci_config.h
deleted file mode 100644 (file)
index ebe0408..0000000
--- a/drivers/gpu/drm/i915/intel_pci_config.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/* SPDX-License-Identifier: MIT */
-/*
- * Copyright © 2022 Intel Corporation
- */
-
-#ifndef __INTEL_PCI_CONFIG_H__
-#define __INTEL_PCI_CONFIG_H__
-
-/* PCI BARs */
-#define GEN2_GMADR_BAR                         0
-#define GEN2_MMADR_BAR                         1 /* MMIO+GTT, despite the name */
-#define GEN2_IO_BAR                            2 /* 85x/865 */
-
-#define GEN3_MMADR_BAR                         0 /* MMIO only */
-#define GEN3_IO_BAR                            1
-#define GEN3_GMADR_BAR                         2
-#define GEN3_GTTADR_BAR                                3 /* GTT only */
-
-#define GEN4_GTTMMADR_BAR                      0 /* MMIO+GTT */
-#define GEN4_GMADR_BAR                         2
-#define GEN4_IO_BAR                            4
-
-#define GEN12_LMEM_BAR                         2
-
-static inline int intel_mmio_bar(int graphics_ver)
-{
-       switch (graphics_ver) {
-       case 2: return GEN2_MMADR_BAR;
-       case 3: return GEN3_MMADR_BAR;
-       default: return GEN4_GTTMMADR_BAR;
-       }
-}
-
-/* BSM in include/drm/intel/i915_drm.h */
-
-#define MCHBAR_I915                            0x44
-#define MCHBAR_I965                            0x48
-#define   MCHBAR_SIZE                          (4 * 4096)
-
-#define DEVEN                                  0x54
-#define   DEVEN_MCHBAR_EN                      (1 << 28)
-
-#define HPLLCC                                 0xc0 /* 85x only */
-#define   GC_CLOCK_CONTROL_MASK                        (0x7 << 0)
-#define   GC_CLOCK_133_200                     (0 << 0)
-#define   GC_CLOCK_100_200                     (1 << 0)
-#define   GC_CLOCK_100_133                     (2 << 0)
-#define   GC_CLOCK_133_266                     (3 << 0)
-#define   GC_CLOCK_133_200_2                   (4 << 0)
-#define   GC_CLOCK_133_266_2                   (5 << 0)
-#define   GC_CLOCK_166_266                     (6 << 0)
-#define   GC_CLOCK_166_250                     (7 << 0)
-
-#define I915_GDRST                             0xc0
-#define   GRDOM_FULL                           (0 << 2)
-#define   GRDOM_RENDER                         (1 << 2)
-#define   GRDOM_MEDIA                          (3 << 2)
-#define   GRDOM_MASK                           (3 << 2)
-#define   GRDOM_RESET_STATUS                   (1 << 1)
-#define   GRDOM_RESET_ENABLE                   (1 << 0)
-
-/* BSpec only has register offset, PCI device and bit found empirically */
-#define I830_CLOCK_GATE                                0xc8 /* device 0 */
-#define   I830_L2_CACHE_CLOCK_GATE_DISABLE     (1 << 2)
-
-#define GCDGMBUS                               0xcc
-
-#define GCFGC2                                 0xda
-#define GCFGC                                  0xf0 /* 915+ only */
-#define   GC_LOW_FREQUENCY_ENABLE              (1 << 7)
-#define   GC_DISPLAY_CLOCK_190_200_MHZ         (0 << 4)
-#define   GC_DISPLAY_CLOCK_333_320_MHZ         (4 << 4)
-#define   GC_DISPLAY_CLOCK_267_MHZ_PNV         (0 << 4)
-#define   GC_DISPLAY_CLOCK_333_MHZ_PNV         (1 << 4)
-#define   GC_DISPLAY_CLOCK_444_MHZ_PNV         (2 << 4)
-#define   GC_DISPLAY_CLOCK_200_MHZ_PNV         (5 << 4)
-#define   GC_DISPLAY_CLOCK_133_MHZ_PNV         (6 << 4)
-#define   GC_DISPLAY_CLOCK_167_MHZ_PNV         (7 << 4)
-#define   GC_DISPLAY_CLOCK_MASK                        (7 << 4)
-#define   GM45_GC_RENDER_CLOCK_MASK            (0xf << 0)
-#define   GM45_GC_RENDER_CLOCK_266_MHZ         (8 << 0)
-#define   GM45_GC_RENDER_CLOCK_320_MHZ         (9 << 0)
-#define   GM45_GC_RENDER_CLOCK_400_MHZ         (0xb << 0)
-#define   GM45_GC_RENDER_CLOCK_533_MHZ         (0xc << 0)
-#define   I965_GC_RENDER_CLOCK_MASK            (0xf << 0)
-#define   I965_GC_RENDER_CLOCK_267_MHZ         (2 << 0)
-#define   I965_GC_RENDER_CLOCK_333_MHZ         (3 << 0)
-#define   I965_GC_RENDER_CLOCK_444_MHZ         (4 << 0)
-#define   I965_GC_RENDER_CLOCK_533_MHZ         (5 << 0)
-#define   I945_GC_RENDER_CLOCK_MASK            (7 << 0)
-#define   I945_GC_RENDER_CLOCK_166_MHZ         (0 << 0)
-#define   I945_GC_RENDER_CLOCK_200_MHZ         (1 << 0)
-#define   I945_GC_RENDER_CLOCK_250_MHZ         (3 << 0)
-#define   I945_GC_RENDER_CLOCK_400_MHZ         (5 << 0)
-#define   I915_GC_RENDER_CLOCK_MASK            (7 << 0)
-#define   I915_GC_RENDER_CLOCK_166_MHZ         (0 << 0)
-#define   I915_GC_RENDER_CLOCK_200_MHZ         (1 << 0)
-#define   I915_GC_RENDER_CLOCK_333_MHZ         (4 << 0)
-
-#define ASLE                                   0xe4
-#define ASLS                                   0xfc
-
-#define SWSCI                                  0xe8
-#define   SWSCI_SCISEL                         (1 << 15)
-#define   SWSCI_GSSCIE                         (1 << 0)
-
-/* legacy/combination backlight modes, also called LBB */
-#define LBPC                                   0xf4
-
-#endif /* __INTEL_PCI_CONFIG_H__ */

diff --git a/drivers/gpu/drm/xe/compat-i915-headers/intel_pci_config.h b/drivers/gpu/drm/xe/compat-i915-headers/intel_pci_config.h
deleted file mode 100644 (file)
index 8c15867..0000000
--- a/drivers/gpu/drm/xe/compat-i915-headers/intel_pci_config.h
+++ /dev/null
@@ -1,6 +0,0 @@
-/* SPDX-License-Identifier: MIT */
-/*
- * Copyright © 2023 Intel Corporation
- */
-
-#include "../../i915/intel_pci_config.h"

diff --git a/include/drm/intel/pci_config.h b/include/drm/intel/pci_config.h
new file mode 100644 (file)
index 0000000..ebe0408
--- /dev/null
+++ b/include/drm/intel/pci_config.h
@@ -0,0 +1,110 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __INTEL_PCI_CONFIG_H__
+#define __INTEL_PCI_CONFIG_H__
+
+/* PCI BARs */
+#define GEN2_GMADR_BAR                         0
+#define GEN2_MMADR_BAR                         1 /* MMIO+GTT, despite the name */
+#define GEN2_IO_BAR                            2 /* 85x/865 */
+
+#define GEN3_MMADR_BAR                         0 /* MMIO only */
+#define GEN3_IO_BAR                            1
+#define GEN3_GMADR_BAR                         2
+#define GEN3_GTTADR_BAR                                3 /* GTT only */
+
+#define GEN4_GTTMMADR_BAR                      0 /* MMIO+GTT */
+#define GEN4_GMADR_BAR                         2
+#define GEN4_IO_BAR                            4
+
+#define GEN12_LMEM_BAR                         2
+
+static inline int intel_mmio_bar(int graphics_ver)
+{
+       switch (graphics_ver) {
+       case 2: return GEN2_MMADR_BAR;
+       case 3: return GEN3_MMADR_BAR;
+       default: return GEN4_GTTMMADR_BAR;
+       }
+}
+
+/* BSM in include/drm/intel/i915_drm.h */
+
+#define MCHBAR_I915                            0x44
+#define MCHBAR_I965                            0x48
+#define   MCHBAR_SIZE                          (4 * 4096)
+
+#define DEVEN                                  0x54
+#define   DEVEN_MCHBAR_EN                      (1 << 28)
+
+#define HPLLCC                                 0xc0 /* 85x only */
+#define   GC_CLOCK_CONTROL_MASK                        (0x7 << 0)
+#define   GC_CLOCK_133_200                     (0 << 0)
+#define   GC_CLOCK_100_200                     (1 << 0)
+#define   GC_CLOCK_100_133                     (2 << 0)
+#define   GC_CLOCK_133_266                     (3 << 0)
+#define   GC_CLOCK_133_200_2                   (4 << 0)
+#define   GC_CLOCK_133_266_2                   (5 << 0)
+#define   GC_CLOCK_166_266                     (6 << 0)
+#define   GC_CLOCK_166_250                     (7 << 0)
+
+#define I915_GDRST                             0xc0
+#define   GRDOM_FULL                           (0 << 2)
+#define   GRDOM_RENDER                         (1 << 2)
+#define   GRDOM_MEDIA                          (3 << 2)
+#define   GRDOM_MASK                           (3 << 2)
+#define   GRDOM_RESET_STATUS                   (1 << 1)
+#define   GRDOM_RESET_ENABLE                   (1 << 0)
+
+/* BSpec only has register offset, PCI device and bit found empirically */
+#define I830_CLOCK_GATE                                0xc8 /* device 0 */
+#define   I830_L2_CACHE_CLOCK_GATE_DISABLE     (1 << 2)
+
+#define GCDGMBUS                               0xcc
+
+#define GCFGC2                                 0xda
+#define GCFGC                                  0xf0 /* 915+ only */
+#define   GC_LOW_FREQUENCY_ENABLE              (1 << 7)
+#define   GC_DISPLAY_CLOCK_190_200_MHZ         (0 << 4)
+#define   GC_DISPLAY_CLOCK_333_320_MHZ         (4 << 4)
+#define   GC_DISPLAY_CLOCK_267_MHZ_PNV         (0 << 4)
+#define   GC_DISPLAY_CLOCK_333_MHZ_PNV         (1 << 4)
+#define   GC_DISPLAY_CLOCK_444_MHZ_PNV         (2 << 4)
+#define   GC_DISPLAY_CLOCK_200_MHZ_PNV         (5 << 4)
+#define   GC_DISPLAY_CLOCK_133_MHZ_PNV         (6 << 4)
+#define   GC_DISPLAY_CLOCK_167_MHZ_PNV         (7 << 4)
+#define   GC_DISPLAY_CLOCK_MASK                        (7 << 4)
+#define   GM45_GC_RENDER_CLOCK_MASK            (0xf << 0)
+#define   GM45_GC_RENDER_CLOCK_266_MHZ         (8 << 0)
+#define   GM45_GC_RENDER_CLOCK_320_MHZ         (9 << 0)
+#define   GM45_GC_RENDER_CLOCK_400_MHZ         (0xb << 0)
+#define   GM45_GC_RENDER_CLOCK_533_MHZ         (0xc << 0)
+#define   I965_GC_RENDER_CLOCK_MASK            (0xf << 0)
+#define   I965_GC_RENDER_CLOCK_267_MHZ         (2 << 0)
+#define   I965_GC_RENDER_CLOCK_333_MHZ         (3 << 0)
+#define   I965_GC_RENDER_CLOCK_444_MHZ         (4 << 0)
+#define   I965_GC_RENDER_CLOCK_533_MHZ         (5 << 0)
+#define   I945_GC_RENDER_CLOCK_MASK            (7 << 0)
+#define   I945_GC_RENDER_CLOCK_166_MHZ         (0 << 0)
+#define   I945_GC_RENDER_CLOCK_200_MHZ         (1 << 0)
+#define   I945_GC_RENDER_CLOCK_250_MHZ         (3 << 0)
+#define   I945_GC_RENDER_CLOCK_400_MHZ         (5 << 0)
+#define   I915_GC_RENDER_CLOCK_MASK            (7 << 0)
+#define   I915_GC_RENDER_CLOCK_166_MHZ         (0 << 0)
+#define   I915_GC_RENDER_CLOCK_200_MHZ         (1 << 0)
+#define   I915_GC_RENDER_CLOCK_333_MHZ         (4 << 0)
+
+#define ASLE                                   0xe4
+#define ASLS                                   0xfc
+
+#define SWSCI                                  0xe8
+#define   SWSCI_SCISEL                         (1 << 15)
+#define   SWSCI_GSSCIE                         (1 << 0)
+
+/* legacy/combination backlight modes, also called LBB */
+#define LBPC                                   0xf4
+
+#endif /* __INTEL_PCI_CONFIG_H__ */