[SPARC64]: Patch up mmu context register writes for sun4v.

sun4v uses ASI_MMU instead of ASI_DMMU

Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/arch/sparc64/kernel/entry.S b/arch/sparc64/kernel/entry.S
index 4ca3ea0..f51b66a 100644 (file)
--- a/arch/sparc64/kernel/entry.S
+++ b/arch/sparc64/kernel/entry.S
@@ -97,10 +97,22 @@ do_fpdis:
        add             %g6, TI_FPREGS + 0x80, %g1
        faddd           %f0, %f2, %f4
        fmuld           %f0, %f2, %f6
-       ldxa            [%g3] ASI_DMMU, %g5
+
+661:   ldxa            [%g3] ASI_DMMU, %g5
+       .section        .sun4v_1insn_patch, "ax"
+       .word           661b
+       ldxa            [%g3] ASI_MMU, %g5
+       .previous
+
        sethi           %hi(sparc64_kern_sec_context), %g2
        ldx             [%g2 + %lo(sparc64_kern_sec_context)], %g2
-       stxa            %g2, [%g3] ASI_DMMU
+
+661:   stxa            %g2, [%g3] ASI_DMMU
+       .section        .sun4v_1insn_patch, "ax"
+       .word           661b
+       stxa            %g2, [%g3] ASI_MMU
+       .previous
+
        membar          #Sync
        add             %g6, TI_FPREGS + 0xc0, %g2
        faddd           %f0, %f2, %f8
@@ -126,11 +138,23 @@ do_fpdis:
         fzero          %f32
        mov             SECONDARY_CONTEXT, %g3
        fzero           %f34
-       ldxa            [%g3] ASI_DMMU, %g5
+
+661:   ldxa            [%g3] ASI_DMMU, %g5
+       .section        .sun4v_1insn_patch, "ax"
+       .word           661b
+       ldxa            [%g3] ASI_MMU, %g5
+       .previous
+
        add             %g6, TI_FPREGS, %g1
        sethi           %hi(sparc64_kern_sec_context), %g2
        ldx             [%g2 + %lo(sparc64_kern_sec_context)], %g2
-       stxa            %g2, [%g3] ASI_DMMU
+
+661:   stxa            %g2, [%g3] ASI_DMMU
+       .section        .sun4v_1insn_patch, "ax"
+       .word           661b
+       stxa            %g2, [%g3] ASI_MMU
+       .previous
+
        membar          #Sync
        add             %g6, TI_FPREGS + 0x40, %g2
        faddd           %f32, %f34, %f36
@@ -155,10 +179,22 @@ do_fpdis:
         nop
 3:     mov             SECONDARY_CONTEXT, %g3
        add             %g6, TI_FPREGS, %g1
-       ldxa            [%g3] ASI_DMMU, %g5
+
+661:   ldxa            [%g3] ASI_DMMU, %g5
+       .section        .sun4v_1insn_patch, "ax"
+       .word           661b
+       ldxa            [%g3] ASI_MMU, %g5
+       .previous
+
        sethi           %hi(sparc64_kern_sec_context), %g2
        ldx             [%g2 + %lo(sparc64_kern_sec_context)], %g2
-       stxa            %g2, [%g3] ASI_DMMU
+
+661:   stxa            %g2, [%g3] ASI_DMMU
+       .section        .sun4v_1insn_patch, "ax"
+       .word           661b
+       stxa            %g2, [%g3] ASI_MMU
+       .previous
+
        membar          #Sync
        mov             0x40, %g2
        membar          #Sync
@@ -169,7 +205,13 @@ do_fpdis:
        ldda            [%g1 + %g2] ASI_BLK_S, %f48
        membar          #Sync
 fpdis_exit:
-       stxa            %g5, [%g3] ASI_DMMU
+
+661:   stxa            %g5, [%g3] ASI_DMMU
+       .section        .sun4v_1insn_patch, "ax"
+       .word           661b
+       stxa            %g5, [%g3] ASI_MMU
+       .previous
+
        membar          #Sync
 fpdis_exit2:
        wr              %g7, 0, %gsr
@@ -323,10 +365,22 @@ do_fptrap_after_fsr:
        rd              %gsr, %g3
        stx             %g3, [%g6 + TI_GSR]
        mov             SECONDARY_CONTEXT, %g3
-       ldxa            [%g3] ASI_DMMU, %g5
+
+661:   ldxa            [%g3] ASI_DMMU, %g5
+       .section        .sun4v_1insn_patch, "ax"
+       .word           661b
+       ldxa            [%g3] ASI_MMU, %g5
+       .previous
+
        sethi           %hi(sparc64_kern_sec_context), %g2
        ldx             [%g2 + %lo(sparc64_kern_sec_context)], %g2
-       stxa            %g2, [%g3] ASI_DMMU
+
+661:   stxa            %g2, [%g3] ASI_DMMU
+       .section        .sun4v_1insn_patch, "ax"
+       .word           661b
+       stxa            %g2, [%g3] ASI_MMU
+       .previous
+
        membar          #Sync
        add             %g6, TI_FPREGS, %g2
        andcc           %g1, FPRS_DL, %g0
@@ -341,7 +395,13 @@ do_fptrap_after_fsr:
        stda            %f48, [%g2 + %g3] ASI_BLK_S
 5:     mov             SECONDARY_CONTEXT, %g1
        membar          #Sync
-       stxa            %g5, [%g1] ASI_DMMU
+
+661:   stxa            %g5, [%g1] ASI_DMMU
+       .section        .sun4v_1insn_patch, "ax"
+       .word           661b
+       stxa            %g5, [%g1] ASI_MMU
+       .previous
+
        membar          #Sync
        ba,pt           %xcc, etrap
         wr             %g0, 0, %fprs

diff --git a/arch/sparc64/kernel/etrap.S b/arch/sparc64/kernel/etrap.S
index d8c062a..a0e7d48 100644 (file)
--- a/arch/sparc64/kernel/etrap.S
+++ b/arch/sparc64/kernel/etrap.S
@@ -95,7 +95,13 @@ etrap_save:  save    %g2, -STACK_BIAS, %sp
                wrpr    %g2, 0, %wstate
                sethi   %hi(sparc64_kern_pri_context), %g2
                ldx     [%g2 + %lo(sparc64_kern_pri_context)], %g3
-               stxa    %g3, [%l4] ASI_DMMU
+
+661:           stxa    %g3, [%l4] ASI_DMMU
+               .section .sun4v_1insn_patch, "ax"
+               .word   661b
+               stxa    %g3, [%l4] ASI_MMU
+               .previous
+
                sethi   %hi(KERNBASE), %l4
                flush   %l4
                mov     ASI_AIUS, %l7

diff --git a/arch/sparc64/kernel/head.S b/arch/sparc64/kernel/head.S
index f04f739..a304845 100644 (file)
--- a/arch/sparc64/kernel/head.S
+++ b/arch/sparc64/kernel/head.S
@@ -303,12 +303,24 @@ jump_to_sun4u_init:
 
 sun4u_init:
        /* Set ctx 0 */
-       mov     PRIMARY_CONTEXT, %g7
-       stxa    %g0, [%g7] ASI_DMMU
-       membar  #Sync
+       mov             PRIMARY_CONTEXT, %g7
+
+661:   stxa            %g0, [%g7] ASI_DMMU
+       .section        .sun4v_1insn_patch, "ax"
+       .word           661b
+       stxa            %g0, [%g7] ASI_MMU
+       .previous
+
+       membar          #Sync
+
+       mov             SECONDARY_CONTEXT, %g7
+
+661:   stxa            %g0, [%g7] ASI_DMMU
+       .section        .sun4v_1insn_patch, "ax"
+       .word           661b
+       stxa            %g0, [%g7] ASI_MMU
+       .previous
 
-       mov     SECONDARY_CONTEXT, %g7
-       stxa    %g0, [%g7] ASI_DMMU
        membar  #Sync
 
        BRANCH_IF_ANY_CHEETAH(g1,g7,cheetah_tlb_fixup)
@@ -436,8 +448,15 @@ setup_trap_table:
        /* Start using proper page size encodings in ctx register.  */
        sethi   %hi(sparc64_kern_pri_context), %g3
        ldx     [%g3 + %lo(sparc64_kern_pri_context)], %g2
-       mov     PRIMARY_CONTEXT, %g1
-       stxa    %g2, [%g1] ASI_DMMU
+
+       mov             PRIMARY_CONTEXT, %g1
+
+661:   stxa            %g2, [%g1] ASI_DMMU
+       .section        .sun4v_1insn_patch, "ax"
+       .word           661b
+       stxa            %g2, [%g1] ASI_MMU
+       .previous
+
        membar  #Sync
 
        /* Kill PROM timer */

diff --git a/arch/sparc64/kernel/rtrap.S b/arch/sparc64/kernel/rtrap.S
index a55d517..551f719 100644 (file)
--- a/arch/sparc64/kernel/rtrap.S
+++ b/arch/sparc64/kernel/rtrap.S
@@ -264,11 +264,23 @@ rt_continue:      ldx                     [%sp + PTREGS_OFF + PT_V9_G1], %g1
 
                brnz,pn                 %l3, kern_rtt
                 mov                    PRIMARY_CONTEXT, %l7
-               ldxa                    [%l7 + %l7] ASI_DMMU, %l0
+
+661:           ldxa                    [%l7 + %l7] ASI_DMMU, %l0
+               .section                .sun4v_1insn_patch, "ax"
+               .word                   661b
+               ldxa                    [%l7 + %l7] ASI_MMU, %l0
+               .previous
+
                sethi                   %hi(sparc64_kern_pri_nuc_bits), %l1
                ldx                     [%l1 + %lo(sparc64_kern_pri_nuc_bits)], %l1
                or                      %l0, %l1, %l0
-               stxa                    %l0, [%l7] ASI_DMMU
+
+661:           stxa                    %l0, [%l7] ASI_DMMU
+               .section                .sun4v_1insn_patch, "ax"
+               .word                   661b
+               stxa                    %l0, [%l7] ASI_MMU
+               .previous
+
                sethi                   %hi(KERNBASE), %l7
                flush                   %l7
                rdpr                    %wstate, %l1
@@ -303,7 +315,13 @@ user_rtt_fill_fixup:
                sethi   %hi(sparc64_kern_pri_context), %g2
                ldx     [%g2 + %lo(sparc64_kern_pri_context)], %g2
                mov     PRIMARY_CONTEXT, %g1
-               stxa    %g2, [%g1] ASI_DMMU
+
+661:           stxa    %g2, [%g1] ASI_DMMU
+               .section .sun4v_1insn_patch, "ax"
+               .word   661b
+               stxa    %g2, [%g1] ASI_MMU
+               .previous
+
                sethi   %hi(KERNBASE), %g1
                flush   %g1
 

diff --git a/arch/sparc64/kernel/setup.c b/arch/sparc64/kernel/setup.c
index 6d6178e..2d64320 100644 (file)
--- a/arch/sparc64/kernel/setup.c
+++ b/arch/sparc64/kernel/setup.c
@@ -189,26 +189,30 @@ int prom_callback(long *args)
                }
 
                if ((va >= KERNBASE) && (va < (KERNBASE + (4 * 1024 * 1024)))) {
-                       extern unsigned long sparc64_kern_pri_context;
-
-                       /* Spitfire Errata #32 workaround */
-                       __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
-                                            "flush     %%g6"
-                                            : /* No outputs */
-                                            : "r" (sparc64_kern_pri_context),
-                                              "r" (PRIMARY_CONTEXT),
-                                              "i" (ASI_DMMU));
+                       if (tlb_type == spitfire) {
+                               extern unsigned long sparc64_kern_pri_context;
+
+                               /* Spitfire Errata #32 workaround */
+                               __asm__ __volatile__(
+                                       "stxa   %0, [%1] %2\n\t"
+                                       "flush  %%g6"
+                                       : /* No outputs */
+                                       : "r" (sparc64_kern_pri_context),
+                                         "r" (PRIMARY_CONTEXT),
+                                         "i" (ASI_DMMU));
+                       }
 
                        /*
                         * Locked down tlb entry.
                         */
 
-                       if (tlb_type == spitfire)
+                       if (tlb_type == spitfire) {
                                tte = spitfire_get_dtlb_data(SPITFIRE_HIGHEST_LOCKED_TLBENT);
-                       else if (tlb_type == cheetah || tlb_type == cheetah_plus)
+                               res = PROM_TRUE;
+                       } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
                                tte = cheetah_get_ldtlb_data(CHEETAH_HIGHEST_LOCKED_TLBENT);
-
-                       res = PROM_TRUE;
+                               res = PROM_TRUE;
+                       }
                        goto done;
                }
 

diff --git a/arch/sparc64/kernel/trampoline.S b/arch/sparc64/kernel/trampoline.S
index 18c333f..d9e2af3 100644 (file)
--- a/arch/sparc64/kernel/trampoline.S
+++ b/arch/sparc64/kernel/trampoline.S
@@ -272,10 +272,22 @@ do_unlock:
        wr              %g0, ASI_P, %asi
 
        mov             PRIMARY_CONTEXT, %g7
-       stxa            %g0, [%g7] ASI_DMMU
+
+661:   stxa            %g0, [%g7] ASI_DMMU
+       .section        .sun4v_1insn_patch, "ax"
+       .word           661b
+       stxa            %g0, [%g7] ASI_MMU
+       .previous
+
        membar          #Sync
        mov             SECONDARY_CONTEXT, %g7
-       stxa            %g0, [%g7] ASI_DMMU
+
+661:   stxa            %g0, [%g7] ASI_DMMU
+       .section        .sun4v_1insn_patch, "ax"
+       .word           661b
+       stxa            %g0, [%g7] ASI_MMU
+       .previous
+
        membar          #Sync
 
        mov             1, %g5
@@ -301,11 +313,17 @@ do_unlock:
         nop
 
        /* Start using proper page size encodings in ctx register.  */
-       sethi   %hi(sparc64_kern_pri_context), %g3
-       ldx     [%g3 + %lo(sparc64_kern_pri_context)], %g2
-       mov     PRIMARY_CONTEXT, %g1
-       stxa    %g2, [%g1] ASI_DMMU
-       membar  #Sync
+       sethi           %hi(sparc64_kern_pri_context), %g3
+       ldx             [%g3 + %lo(sparc64_kern_pri_context)], %g2
+       mov             PRIMARY_CONTEXT, %g1
+
+661:   stxa            %g2, [%g1] ASI_DMMU
+       .section        .sun4v_1insn_patch, "ax"
+       .word           661b
+       stxa            %g2, [%g1] ASI_MMU
+       .previous
+
+       membar          #Sync
 
        rdpr            %pstate, %o1
        or              %o1, PSTATE_IE, %o1

diff --git a/arch/sparc64/mm/init.c b/arch/sparc64/mm/init.c
index 4c95cf3..6504d6e 100644 (file)
--- a/arch/sparc64/mm/init.c
+++ b/arch/sparc64/mm/init.c
@@ -792,15 +792,6 @@ void sparc_ultra_dump_dtlb(void)
        }
 }
 
-static inline void spitfire_errata32(void)
-{
-       __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
-                            "flush     %%g6"
-                            : /* No outputs */
-                            : "r" (0),
-                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
-}
-
 extern unsigned long cmdline_memory_size;
 
 unsigned long __init bootmem_init(unsigned long *pages_avail)

diff --git a/arch/sparc64/prom/p1275.c b/arch/sparc64/prom/p1275.c
index a5a7c57..2b32c48 100644 (file)
--- a/arch/sparc64/prom/p1275.c
+++ b/arch/sparc64/prom/p1275.c
@@ -30,16 +30,6 @@ extern void prom_world(int);
 extern void prom_cif_interface(void);
 extern void prom_cif_callback(void);
 
-static inline unsigned long spitfire_get_primary_context(void)
-{
-       unsigned long ctx;
-
-       __asm__ __volatile__("ldxa      [%1] %2, %0"
-                            : "=r" (ctx)
-                            : "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
-       return ctx;
-}
-
 /*
  * This provides SMP safety on the p1275buf. prom_callback() drops this lock
  * to allow recursuve acquisition.
@@ -55,7 +45,6 @@ long p1275_cmd(const char *service, long fmt, ...)
        long attrs, x;
        
        p = p1275buf.prom_buffer;
-       BUG_ON((spitfire_get_primary_context() & CTX_NR_MASK) != 0);
 
        spin_lock_irqsave(&prom_entry_lock, flags);
 

diff --git a/include/asm-sparc64/mmu_context.h b/include/asm-sparc64/mmu_context.h
index 1d23267..2760353 100644 (file)
--- a/include/asm-sparc64/mmu_context.h
+++ b/include/asm-sparc64/mmu_context.h
@@ -41,11 +41,16 @@ extern void smp_tsb_sync(struct mm_struct *mm);
 
 /* Set MMU context in the actual hardware. */
 #define load_secondary_context(__mm) \
-       __asm__ __volatile__("stxa      %0, [%1] %2\n\t" \
-                            "flush     %%g6" \
-                            : /* No outputs */ \
-                            : "r" (CTX_HWBITS((__mm)->context)), \
-                              "r" (SECONDARY_CONTEXT), "i" (ASI_DMMU))
+       __asm__ __volatile__( \
+       "\n661: stxa            %0, [%1] %2\n" \
+       "       .section        .sun4v_1insn_patch, \"ax\"\n" \
+       "       .word           661b\n" \
+       "       stxa            %0, [%1] %3\n" \
+       "       .previous\n" \
+       "       flush           %%g6\n" \
+       : /* No outputs */ \
+       : "r" (CTX_HWBITS((__mm)->context)), \
+         "r" (SECONDARY_CONTEXT), "i" (ASI_DMMU), "i" (ASI_MMU))
 
 extern void __flush_tlb_mm(unsigned long, unsigned long);