arm64: tegra: Device tree changes for v5.6-rc1
These patches do some cleanup to existing nodes, add the memory
subsystem on Tegra186 and Tegra194 as well as the FUSE and APB MISC
nodes on Tegra194. There are also a few additions to the Jetson Nano
device tree to enable additional features and the force recovery
button on the Jetson AGX Xavier now produces a key code that is
actually valid. Finally, an alias is added for the Ethernet card on
Jetson TX2 to allow firmware to find it and pass a MAC address via
device tree.
* tag 'tegra-for-5.6-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
arm64: tegra: Allow bootloader to configure Ethernet MAC on Jetson TX2
arm64: tegra: Redefine force recovery key on Jetson AGX Xavier
arm64: tegra: Enable SDIO on Jetson Nano M.2 Key E
arm64: tegra: Enable PWM fan on Jetson Nano
arm64: tegra: Add fuse/apbmisc node on Tegra194
arm64: tegra: Make XUSB node consistent with the rest
arm64: tegra: Add the memory subsystem on Tegra194
arm64: tegra: Add external memory controller on Tegra186
arm64: tegra: Add interrupt for memory controller on Tegra186
arm64: tegra: Rename EMC on Tegra132
arm64: tegra: Let the EMC hardware use the EMC clock
Link: https://lore.kernel.org/r/20200111003553.2411874-7-thierry.reding@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
#iommu-cells = <1>;
};
- emc: emc@7001b000 {
+ emc: external-memory-controller@7001b000 {
compatible = "nvidia,tegra132-emc", "nvidia,tegra124-emc";
reg = <0x0 0x7001b000 0x0 0x1000>;
+ clocks = <&tegra_car TEGRA124_CLK_EMC>;
+ clock-names = "emc";
nvidia,memory-controller = <&mc>;
};
compatible = "nvidia,p3310", "nvidia,tegra186";
aliases {
+ ethernet0 = "/ethernet@2490000";
sdhci0 = "/sdhci@3460000";
sdhci1 = "/sdhci@3400000";
serial0 = &uarta;
memory-controller@2c00000 {
compatible = "nvidia,tegra186-mc";
reg = <0x0 0x02c00000 0x0 0xb0000>;
+ interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>;
+
+ /*
+ * Memory clients have access to all 40 bits that the memory
+ * controller can address.
+ */
+ dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
+
+ emc: external-memory-controller@2c60000 {
+ compatible = "nvidia,tegra186-emc";
+ reg = <0x0 0x02c60000 0x0 0x50000>;
+ interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA186_CLK_EMC>;
+ clock-names = "emc";
+
+ nvidia,bpmp = <&bpmp>;
+ };
};
uarta: serial@3100000 {
reg = <0x0 0x03530000 0x0 0x8000>,
<0x0 0x03538000 0x0 0x1000>;
reg-names = "hcd", "fpci";
-
- iommus = <&smmu TEGRA186_SID_XUSB_HOST>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
-
clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>,
<&bpmp TEGRA186_CLK_XUSB_FALCON>,
<&bpmp TEGRA186_CLK_XUSB_SS>,
clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss",
"xusb_ss_src", "xusb_hs_src", "xusb_fs_src",
"pll_u_480m", "clk_m", "pll_e";
-
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>,
<&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
power-domain-names = "xusb_host", "xusb_ss";
- nvidia,xusb-padctl = <&padctl>;
-
- status = "disabled";
-
+ iommus = <&smmu TEGRA186_SID_XUSB_HOST>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
+
+ nvidia,xusb-padctl = <&padctl>;
};
fuse@3820000 {
};
};
+ memory-controller@2c00000 {
+ status = "okay";
+ };
+
serial@3110000 {
status = "okay";
};
gpios = <&gpio TEGRA194_MAIN_GPIO(G, 0)
GPIO_ACTIVE_LOW>;
linux,input-type = <EV_KEY>;
- linux,code = <BTN_1>;
+ linux,code = <KEY_SLEEP>;
debounce-interval = <10>;
};
#include <dt-bindings/power/tegra194-powergate.h>
#include <dt-bindings/reset/tegra194-reset.h>
#include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
+#include <dt-bindings/memory/tegra194-mc.h>
/ {
compatible = "nvidia,tegra194";
#size-cells = <1>;
ranges = <0x0 0x0 0x0 0x40000000>;
+ misc@100000 {
+ compatible = "nvidia,tegra194-misc";
+ reg = <0x00100000 0xf000>,
+ <0x0010f000 0x1000>;
+ };
+
gpio: gpio@2200000 {
compatible = "nvidia,tegra194-gpio";
reg-names = "security", "gpio";
};
};
+ mc: memory-controller@2c00000 {
+ compatible = "nvidia,tegra194-mc";
+ reg = <0x02c00000 0x100000>,
+ <0x02b80000 0x040000>,
+ <0x01700000 0x100000>;
+ status = "disabled";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>,
+ <0x02b80000 0x0 0x02b80000 0x0 0x040000>,
+ <0x02c00000 0x0 0x02c00000 0x0 0x100000>;
+
+ /*
+ * Bit 39 of addresses passing through the memory
+ * controller selects the XBAR format used when memory
+ * is accessed. This is used to transparently access
+ * memory in the XBAR format used by the discrete GPU
+ * (bit 39 set) or Tegra (bit 39 clear).
+ *
+ * As a consequence, the operating system must ensure
+ * that bit 39 is never used implicitly, for example
+ * via an I/O virtual address mapping of an IOMMU. If
+ * devices require access to the XBAR switch, their
+ * drivers must set this bit explicitly.
+ *
+ * Limit the DMA range for memory clients to [38:0].
+ */
+ dma-ranges = <0x0 0x0 0x0 0x80 0x0>;
+
+ emc: external-memory-controller@2c60000 {
+ compatible = "nvidia,tegra194-emc";
+ reg = <0x0 0x02c60000 0x0 0x90000>,
+ <0x0 0x01780000 0x0 0x80000>;
+ clocks = <&bpmp TEGRA194_CLK_EMC>;
+ clock-names = "emc";
+
+ nvidia,bpmp = <&bpmp>;
+ };
+ };
+
uarta: serial@3100000 {
compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
reg = <0x03100000 0x40>;
status = "disabled";
};
+ fuse@3820000 {
+ compatible = "nvidia,tegra194-efuse";
+ reg = <0x03820000 0x10000>;
+ clocks = <&bpmp TEGRA194_CLK_FUSE>;
+ clock-names = "fuse";
+ };
+
gic: interrupt-controller@3881000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
vmmc-supply = <&vdd_3v3_sd>;
};
+ sdhci@700b0400 {
+ status = "okay";
+ bus-width = <4>;
+
+ vqmmc-supply = <&vdd_1v8>;
+ vmmc-supply = <&vdd_3v3_sys>;
+
+ non-removable;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ wakeup-source;
+ };
+
clocks {
compatible = "simple-bus";
#address-cells = <1>;
};
};
+ fan: fan {
+ compatible = "pwm-fan";
+ pwms = <&pwm 3 45334>;
+
+ cooling-levels = <0 64 128 255>;
+ #cooling-cells = <2>;
+ };
+
+ thermal-zones {
+ cpu {
+ trips {
+ cpu_trip_critical: critical {
+ temperature = <96500>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+
+ cpu_trip_hot: hot {
+ temperature = <70000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ cpu_trip_active: active {
+ temperature = <50000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ cpu_trip_passive: passive {
+ temperature = <30000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu-critical {
+ cooling-device = <&fan 3 3>;
+ trip = <&cpu_trip_critical>;
+ };
+
+ cpu-hot {
+ cooling-device = <&fan 2 2>;
+ trip = <&cpu_trip_hot>;
+ };
+
+ cpu-active {
+ cooling-device = <&fan 1 1>;
+ trip = <&cpu_trip_active>;
+ };
+
+ cpu-passive {
+ cooling-device = <&fan 0 0>;
+ trip = <&cpu_trip_passive>;
+ };
+ };
+ };
+ };
+
gpio-keys {
compatible = "gpio-keys";
projects / linux-2.6-microblaze.git / commitdiff