dt-bindings: PCI: exynos: drop samsung,exynos5440-pcie binding

Exynos5440 SoC support has been dropped since commit 8c83315da1cf ("ARM:
dts: exynos: Remove Exynos5440"). Drop the obsolete bindings for
exynos5440-pcie.

Link: https://lore.kernel.org/r/20201113170139.29956-2-m.szyprowski@samsung.com
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Jingoo Han <jingoohan1@gmail.com>

diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
deleted file mode 100644 (file)
index 651d957..0000000
--- a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
+++ /dev/null
@@ -1,58 +0,0 @@
-* Samsung Exynos 5440 PCIe interface
-
-This PCIe host controller is based on the Synopsys DesignWare PCIe IP
-and thus inherits all the common properties defined in designware-pcie.txt.
-
-Required properties:
-- compatible: "samsung,exynos5440-pcie"
-- reg: base addresses and lengths of the PCIe controller,
-- reg-names : First name should be set to "elbi".
-       And use the "config" instead of getting the configuration address space
-       from "ranges".
-       NOTE: When using the "config" property, reg-names must be set.
-- interrupts: A list of interrupt outputs for level interrupt,
-       pulse interrupt, special interrupt.
-- phys: From PHY binding. Phandle for the generic PHY.
-       Refer to Documentation/devicetree/bindings/phy/samsung-phy.txt
-
-For other common properties, refer to
-       Documentation/devicetree/bindings/pci/designware-pcie.txt
-
-Example:
-
-SoC-specific DT Entry (with using PHY framework):
-
-       pcie_phy0: pcie-phy@270000 {
-               ...
-               reg = <0x270000 0x1000>, <0x271000 0x40>;
-               reg-names = "phy", "block";
-               ...
-       };
-
-       pcie@290000 {
-               compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
-               reg = <0x290000 0x1000>, <0x40000000 0x1000>;
-               reg-names = "elbi", "config";
-               clocks = <&clock 28>, <&clock 27>;
-               clock-names = "pcie", "pcie_bus";
-               #address-cells = <3>;
-               #size-cells = <2>;
-               device_type = "pci";
-               phys = <&pcie_phy0>;
-               ranges = <0x81000000 0 0          0x60001000 0 0x00010000
-                         0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>;
-               #interrupt-cells = <1>;
-               interrupt-map-mask = <0 0 0 0>;
-               interrupt-map = <0 0 0 0 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
-               num-lanes = <4>;
-       };
-
-Board-specific DT Entry:
-
-       pcie@290000 {
-               reset-gpio = <&pin_ctrl 5 0>;
-       };
-
-       pcie@2a0000 {
-               reset-gpio = <&pin_ctrl 22 0>;
-       };