arm64: dts: qcom: x1e80100: Fix PCIe 6a lanes description

Fix the description and compatible for PCIe 6a, as it is in fact a
4-lanes controller and PHY, but it can also be used in 2-lanes mode. For
4-lanes mode, it uses the lanes provided by PCIe 6b. For 2-lanes mode,
PCIe 6a uses 2 lanes and then PCIe 6b uses the other 2 lanes. The number
of lanes in which the PHY should be configured depends on a TCSR register
value on each individual board.

Cc: stable+noautosel@kernel.org # Depends on pcie-qcom 16.0 GT/s support
Fixes: 5eb83fc10289 ("arm64: dts: qcom: x1e80100: Add PCIe nodes")
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Tested-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20241009-x1e80100-dts-fixes-pcie6a-v3-1-14a1163e691b@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index 27796ba..6a419fb 100644 (file)
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -2931,7 +2931,7 @@
                        dma-coherent;
 
                        linux,pci-domain = <6>;
-                       num-lanes = <2>;
+                       num-lanes = <4>;
 
                        interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>,
@@ -2997,8 +2997,9 @@
                };
 
                pcie6a_phy: phy@1bfc000 {
-                       compatible = "qcom,x1e80100-qmp-gen4x2-pcie-phy";
-                       reg = <0 0x01bfc000 0 0x2000>;
+                       compatible = "qcom,x1e80100-qmp-gen4x4-pcie-phy";
+                       reg = <0 0x01bfc000 0 0x2000>,
+                             <0 0x01bfe000 0 0x2000>;
 
                        clocks = <&gcc GCC_PCIE_6A_PHY_AUX_CLK>,
                                 <&gcc GCC_PCIE_6A_CFG_AHB_CLK>,
@@ -3023,6 +3024,8 @@
 
                        power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>;
 
+                       qcom,4ln-config-sel = <&tcsr 0x1a000 0>;
+
                        #clock-cells = <0>;
                        clock-output-names = "pcie6a_pipe_clk";