arm64: dts: renesas: r9a08g045: Add IA55 interrupt controller node

Add IA55 interrupt controller node and set it as interrupt parent for pin
controller.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20231120111820.87398-10-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
index 6c7b29b..010bca6 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
@@ -96,6 +96,7 @@
                        #gpio-cells = <2>;
                        interrupt-controller;
                        #interrupt-cells = <2>;
+                       interrupt-parent = <&irqc>;
                        gpio-ranges = <&pinctrl 0 0 152>;
                        clocks = <&cpg CPG_MOD R9A08G045_GPIO_HCLK>;
                        power-domains = <&cpg>;
@@ -104,6 +105,73 @@
                                 <&cpg R9A08G045_GPIO_SPARE_RESETN>;
                };
 
+               irqc: interrupt-controller@11050000 {
+                       compatible = "renesas,r9a08g045-irqc", "renesas,rzg2l-irqc";
+                       #interrupt-cells = <2>;
+                       #address-cells = <0>;
+                       interrupt-controller;
+                       reg = <0 0x11050000 0 0x10000>;
+                       interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "nmi",
+                                         "irq0", "irq1", "irq2", "irq3",
+                                         "irq4", "irq5", "irq6", "irq7",
+                                         "tint0", "tint1", "tint2", "tint3",
+                                         "tint4", "tint5", "tint6", "tint7",
+                                         "tint8", "tint9", "tint10", "tint11",
+                                         "tint12", "tint13", "tint14", "tint15",
+                                         "tint16", "tint17", "tint18", "tint19",
+                                         "tint20", "tint21", "tint22", "tint23",
+                                         "tint24", "tint25", "tint26", "tint27",
+                                         "tint28", "tint29", "tint30", "tint31",
+                                         "bus-err";
+                       clocks = <&cpg CPG_MOD R9A08G045_IA55_CLK>,
+                                <&cpg CPG_MOD R9A08G045_IA55_PCLK>;
+                       clock-names = "clk", "pclk";
+                       power-domains = <&cpg>;
+                       resets = <&cpg R9A08G045_IA55_RESETN>;
+               };
+
                sdhi0: mmc@11c00000  {
                        compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi";
                        reg = <0x0 0x11c00000 0 0x10000>;