drm/amd/display: reset dcn31 SMU mailbox on failures

Otherwise future commands may fail as well leading to downstream
problems that look like they stemmed from a timeout the first time
but really didn't.

Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
index b7ace23..a1011f3 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
@@ -119,6 +119,12 @@ static int dcn31_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,
 
        result = dcn31_smu_wait_for_response(clk_mgr, 10, 200000);
 
+       if (result == VBIOSSMC_Result_Failed) {
+               ASSERT(0);
+               REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Result_OK);
+               return -1;
+       }
+
        if (IS_SMU_TIMEOUT(result)) {
                ASSERT(0);
                dm_helpers_smu_timeout(CTX, msg_id, param, 10 * 200000);