drm/i915: Move DPLL HW readout/sanitize fns to intel_dpll_mgr.c

Move the HW readout/sanitize functions to intel_dpll_mgr.c which
contains the rest of shared DPLL functionality.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200226203455.23032-3-imre.deak@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 2a81212..125d5c0 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -18333,7 +18333,6 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
        struct intel_connector *connector;
        struct drm_connector_list_iter conn_iter;
        u8 active_pipes = 0;
-       int i;
 
        for_each_intel_crtc(dev, crtc) {
                struct intel_crtc_state *crtc_state =
@@ -18362,33 +18361,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
 
        readout_plane_state(dev_priv);
 
-       for (i = 0; i < dev_priv->num_shared_dpll; i++) {
-               struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
-
-               pll->on = pll->info->funcs->get_hw_state(dev_priv, pll,
-                                                       &pll->state.hw_state);
-
-               if (IS_ELKHARTLAKE(dev_priv) && pll->on &&
-                   pll->info->id == DPLL_ID_EHL_DPLL4) {
-                       pll->wakeref = intel_display_power_get(dev_priv,
-                                                              POWER_DOMAIN_DPLL_DC_OFF);
-               }
-
-               pll->state.crtc_mask = 0;
-               for_each_intel_crtc(dev, crtc) {
-                       struct intel_crtc_state *crtc_state =
-                               to_intel_crtc_state(crtc->base.state);
-
-                       if (crtc_state->hw.active &&
-                           crtc_state->shared_dpll == pll)
-                               pll->state.crtc_mask |= 1 << crtc->pipe;
-               }
-               pll->active_mask = pll->state.crtc_mask;
-
-               drm_dbg_kms(&dev_priv->drm,
-                           "%s hw state readout: crtc_mask 0x%08x, on %i\n",
-                           pll->info->name, pll->state.crtc_mask, pll->on);
-       }
+       intel_dpll_readout_hw_state(dev_priv);
 
        for_each_intel_encoder(dev, encoder) {
                pipe = 0;
@@ -18645,7 +18618,6 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
        struct intel_encoder *encoder;
        struct intel_crtc *crtc;
        intel_wakeref_t wakeref;
-       int i;
 
        wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 
@@ -18698,19 +18670,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
 
        intel_modeset_update_connector_atomic_state(dev);
 
-       for (i = 0; i < dev_priv->num_shared_dpll; i++) {
-               struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
-
-               if (!pll->on || pll->active_mask)
-                       continue;
-
-               drm_dbg_kms(&dev_priv->drm,
-                           "%s enabled but not in use, disabling\n",
-                           pll->info->name);
-
-               pll->info->funcs->disable(dev_priv, pll);
-               pll->on = false;
-       }
+       intel_dpll_sanitize_state(dev_priv);
 
        if (IS_G4X(dev_priv)) {
                g4x_wm_get_hw_state(dev_priv);

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 6cf2917..3a937b9 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3919,6 +3919,65 @@ void intel_update_active_dpll(struct intel_atomic_state *state,
        dpll_mgr->update_active_dpll(state, crtc, encoder);
 }
 
+static void readout_dpll_hw_state(struct drm_i915_private *i915,
+                                 struct intel_shared_dpll *pll)
+{
+       struct intel_crtc *crtc;
+
+       pll->on = pll->info->funcs->get_hw_state(i915, pll,
+                                                &pll->state.hw_state);
+
+       if (IS_ELKHARTLAKE(i915) && pll->on &&
+           pll->info->id == DPLL_ID_EHL_DPLL4) {
+               pll->wakeref = intel_display_power_get(i915,
+                                                      POWER_DOMAIN_DPLL_DC_OFF);
+       }
+
+       pll->state.crtc_mask = 0;
+       for_each_intel_crtc(&i915->drm, crtc) {
+               struct intel_crtc_state *crtc_state =
+                       to_intel_crtc_state(crtc->base.state);
+
+               if (crtc_state->hw.active && crtc_state->shared_dpll == pll)
+                       pll->state.crtc_mask |= 1 << crtc->pipe;
+       }
+       pll->active_mask = pll->state.crtc_mask;
+
+       drm_dbg_kms(&i915->drm,
+                   "%s hw state readout: crtc_mask 0x%08x, on %i\n",
+                   pll->info->name, pll->state.crtc_mask, pll->on);
+}
+
+void intel_dpll_readout_hw_state(struct drm_i915_private *i915)
+{
+       int i;
+
+       for (i = 0; i < i915->num_shared_dpll; i++)
+               readout_dpll_hw_state(i915, &i915->shared_dplls[i]);
+}
+
+static void sanitize_dpll_state(struct drm_i915_private *i915,
+                               struct intel_shared_dpll *pll)
+{
+       if (!pll->on || pll->active_mask)
+               return;
+
+       drm_dbg_kms(&i915->drm,
+                   "%s enabled but not in use, disabling\n",
+                   pll->info->name);
+
+       pll->info->funcs->disable(i915, pll);
+       pll->on = false;
+}
+
+void intel_dpll_sanitize_state(struct drm_i915_private *i915)
+{
+       int i;
+
+       for (i = 0; i < i915->num_shared_dpll; i++)
+               sanitize_dpll_state(i915, &i915->shared_dplls[i]);
+}
+
 /**
  * intel_shared_dpll_dump_hw_state - write hw_state to dmesg
  * @dev_priv: i915 drm device

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 2a104c6..fe27a5d 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -377,6 +377,8 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
 void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
 void intel_shared_dpll_swap_state(struct intel_atomic_state *state);
 void intel_shared_dpll_init(struct drm_device *dev);
+void intel_dpll_readout_hw_state(struct drm_i915_private *dev_priv);
+void intel_dpll_sanitize_state(struct drm_i915_private *dev_priv);
 
 void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
                              const struct intel_dpll_hw_state *hw_state);