drm/amd/display: Wait For DET Update Should Use Current State

[Why]
Current state should be used when waiting for DET update
instead of new context.
For any streams decreasing in DET, pipes used in the current state
should be checked since those pipes need to free their DET before
DET can be reallocated.

[How]
Pass in current_state instead of context.
Use pipe from current_state instead of context. This assumes that
pipe in the current_state is an OTG_MASTER pipe if the pipe in the context is an OTG_MASTER pipe.

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Austin Zheng <Austin.Zheng@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index 29fcb4e..805e7b5 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
@@ -1669,7 +1669,7 @@ void dcn401_hardware_release(struct dc *dc)
        }
 }
 
-void dcn401_wait_for_det_buffer_update(struct dc *dc, struct dc_state *context, struct pipe_ctx *otg_master)
+void dcn401_wait_for_det_buffer_update_under_otg_master(struct dc *dc, struct dc_state *context, struct pipe_ctx *otg_master)
 {
        struct pipe_ctx *opp_heads[MAX_PIPES];
        struct pipe_ctx *dpp_pipes[MAX_PIPES];
@@ -1695,6 +1695,9 @@ void dcn401_wait_for_det_buffer_update(struct dc *dc, struct dc_state *context,
                                                hubbub->funcs->wait_for_det_update)
                                                hubbub->funcs->wait_for_det_update(hubbub, dpp_pipe->plane_res.hubp->inst);
                        }
+               } else {
+                       if (hubbub && opp_heads[slice_idx]->plane_res.hubp && hubbub->funcs->wait_for_det_update)
+                               hubbub->funcs->wait_for_det_update(hubbub, opp_heads[slice_idx]->plane_res.hubp->inst);
                }
        }
 }
@@ -1730,8 +1733,10 @@ void dcn401_interdependent_update_lock(struct dc *dc,
                        }
 
                        if (dc->scratch.pipes_to_unlock_first[i]) {
+                               struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
                                dc->hwss.pipe_control_lock(dc, pipe, false);
-                               dcn401_wait_for_det_buffer_update(dc, context, pipe);
+                               /* Assumes pipe of the same index in current_state is also an OTG_MASTER pipe*/
+                               dcn401_wait_for_det_buffer_update_under_otg_master(dc, dc->current_state, old_pipe);
                        }
                }
 

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
index a27e620..1e8189b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
@@ -81,7 +81,7 @@ void dcn401_hardware_release(struct dc *dc);
 void dcn401_update_odm(struct dc *dc, struct dc_state *context,
                struct pipe_ctx *otg_master);
 void adjust_hotspot_between_slices_for_2x_magnify(uint32_t cursor_width, struct dc_cursor_position *pos_cpy);
-void dcn401_wait_for_det_buffer_update(struct dc *dc, struct dc_state *context, struct pipe_ctx *otg_master);
+void dcn401_wait_for_det_buffer_update_under_otg_master(struct dc *dc, struct dc_state *context, struct pipe_ctx *otg_master);
 void dcn401_interdependent_update_lock(struct dc *dc, struct dc_state *context, bool lock);
 void dcn401_program_outstanding_updates(struct dc *dc, struct dc_state *context);
 #endif /* __DC_HWSS_DCN401_H__ */