drm/amdkfd: Fix reg offset for setting CWSR grace period
authorMukul Joshi <mukul.joshi@amd.com>
Mon, 28 Aug 2023 18:18:23 +0000 (14:18 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 11 Sep 2023 22:15:43 +0000 (18:15 -0400)
This patch fixes the case where the code currently passes
absolute register address and not the reg offset, which HWS
expects, when sending the PM4 packet to set/update CWSR grace
period. Additionally, cleanup the signature of
build_grace_period_packet_info function as it no longer needs
the inst parameter.

Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Jonathan Kim <jonathan.kim@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c
drivers/gpu/drm/amd/include/kgd_kfd_interface.h

index f1f2c24..69810b3 100644 (file)
@@ -980,8 +980,7 @@ void kgd_gfx_v10_build_grace_period_packet_info(struct amdgpu_device *adev,
                                                uint32_t wait_times,
                                                uint32_t grace_period,
                                                uint32_t *reg_offset,
-                                               uint32_t *reg_data,
-                                               uint32_t inst)
+                                               uint32_t *reg_data)
 {
        *reg_data = wait_times;
 
index ecaead2..67bcaa3 100644 (file)
@@ -55,5 +55,4 @@ void kgd_gfx_v10_build_grace_period_packet_info(struct amdgpu_device *adev,
                                               uint32_t wait_times,
                                               uint32_t grace_period,
                                               uint32_t *reg_offset,
-                                              uint32_t *reg_data,
-                                              uint32_t inst);
+                                              uint32_t *reg_data);
index fa5ee96..3c45a18 100644 (file)
@@ -1103,8 +1103,7 @@ void kgd_gfx_v9_build_grace_period_packet_info(struct amdgpu_device *adev,
                uint32_t wait_times,
                uint32_t grace_period,
                uint32_t *reg_offset,
-               uint32_t *reg_data,
-               uint32_t inst)
+               uint32_t *reg_data)
 {
        *reg_data = wait_times;
 
@@ -1120,8 +1119,7 @@ void kgd_gfx_v9_build_grace_period_packet_info(struct amdgpu_device *adev,
                        SCH_WAVE,
                        grace_period);
 
-       *reg_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, inst),
-                       mmCP_IQ_WAIT_TIME2);
+       *reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_IQ_WAIT_TIME2);
 }
 
 void kgd_gfx_v9_program_trap_handler_settings(struct amdgpu_device *adev,
index 936e501..ce42461 100644 (file)
@@ -100,5 +100,4 @@ void kgd_gfx_v9_build_grace_period_packet_info(struct amdgpu_device *adev,
                                               uint32_t wait_times,
                                               uint32_t grace_period,
                                               uint32_t *reg_offset,
-                                              uint32_t *reg_data,
-                                              uint32_t inst);
+                                              uint32_t *reg_data);
index b166f30..8a6cb41 100644 (file)
@@ -1677,8 +1677,7 @@ static int start_cpsch(struct device_queue_manager *dqm)
                        dqm->dev->kfd2kgd->build_grace_period_packet_info(
                                        dqm->dev->adev, dqm->wait_times,
                                        grace_period, &reg_offset,
-                                       &dqm->wait_times,
-                                       ffs(dqm->dev->xcc_mask) - 1);
+                                       &dqm->wait_times);
        }
 
        dqm_unlock(dqm);
index 8ce6f52..1a03173 100644 (file)
@@ -299,8 +299,7 @@ static int pm_set_grace_period_v9(struct packet_manager *pm,
                        pm->dqm->wait_times,
                        grace_period,
                        &reg_offset,
-                       &reg_data,
-                       0);
+                       &reg_data);
 
        if (grace_period == USE_DEFAULT_GRACE_PERIOD)
                reg_data = pm->dqm->wait_times;
index 8433f99..f3f40db 100644 (file)
@@ -326,8 +326,7 @@ struct kfd2kgd_calls {
                        uint32_t wait_times,
                        uint32_t grace_period,
                        uint32_t *reg_offset,
-                       uint32_t *reg_data,
-                       uint32_t inst);
+                       uint32_t *reg_data);
        void (*get_cu_occupancy)(struct amdgpu_device *adev, int pasid,
                        int *wave_cnt, int *max_waves_per_cu, uint32_t inst);
        void (*program_trap_handler_settings)(struct amdgpu_device *adev,