static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
{
- enum pipe pipe;
-
if (HAS_LLC(dev_priv)) {
/*
* WaCompressedResourceDisplayNewHashMode:skl,kbl
SKL_DE_COMPRESSED_HASH_MODE);
}
- for_each_pipe(dev_priv, pipe) {
- /*
- * "Plane N strech max must be programmed to 11b (x1)
- * when Async flips are enabled on that plane."
- */
- if (!IS_GEMINILAKE(dev_priv) && intel_vtd_active())
- intel_uncore_rmw(&dev_priv->uncore, CHICKEN_PIPESL_1(pipe),
- SKL_PLANE1_STRETCH_MAX_MASK, SKL_PLANE1_STRETCH_MAX_X1);
- }
-
/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
intel_uncore_write(&dev_priv->uncore, CHICKEN_PAR1_1,
intel_uncore_read(&dev_priv->uncore, CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);