{ .name = "n3000bmc-secure" },
 };
 
+static const struct regmap_range m10bmc_regmap_range[] = {
+       regmap_reg_range(M10BMC_LEGACY_BUILD_VER, M10BMC_LEGACY_BUILD_VER),
+       regmap_reg_range(M10BMC_SYS_BASE, M10BMC_SYS_END),
+       regmap_reg_range(M10BMC_FLASH_BASE, M10BMC_FLASH_END),
+};
+
+static const struct regmap_access_table m10bmc_access_table = {
+       .yes_ranges     = m10bmc_regmap_range,
+       .n_yes_ranges   = ARRAY_SIZE(m10bmc_regmap_range),
+};
+
 static struct regmap_config intel_m10bmc_regmap_config = {
        .reg_bits = 32,
        .val_bits = 32,
        .reg_stride = 4,
+       .wr_table = &m10bmc_access_table,
+       .rd_table = &m10bmc_access_table,
        .max_register = M10BMC_MEM_END,
 };
 
 
 
 #define M10BMC_LEGACY_BUILD_VER                0x300468
 #define M10BMC_SYS_BASE                        0x300800
-#define M10BMC_MEM_END                 0x1fffffff
+#define M10BMC_SYS_END                 0x300fff
+#define M10BMC_FLASH_BASE              0x10000000
+#define M10BMC_FLASH_END               0x1fffffff
+#define M10BMC_MEM_END                 M10BMC_FLASH_END
 
 /* Register offset of system registers */
 #define NIOS2_FW_VERSION               0x0