wifi: iwlwifi: read mac step from aux register
authorMiri Korenblit <miriam.rachel.korenblit@intel.com>
Sun, 4 Feb 2024 22:06:09 +0000 (00:06 +0200)
committerJohannes Berg <johannes.berg@intel.com>
Thu, 8 Feb 2024 14:00:46 +0000 (15:00 +0100)
in BZ, the mac step is not updated to the HW REV CSR.
For BZ-I, read it from the CNVI aux register
For BZ-U always take B step.

Signed-off-by: Miri Korenblit <miriam.rachel.korenblit@intel.com>
Link: https://msgid.link/20240204235836.dcc18b533f13.I0a6267fa0a142744bcf7500b45f667b596b492c5@changeid
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
drivers/net/wireless/intel/iwlwifi/iwl-prph.h
drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info-gen3.c
drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info.c
drivers/net/wireless/intel/iwlwifi/pcie/drv.c

index c1c7d44..a7d44df 100644 (file)
@@ -368,7 +368,11 @@ enum {
        WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK       = 0x80000000,
 };
 
-#define CNVI_AUX_MISC_CHIP                             0xA200B0
+#define CNVI_AUX_MISC_CHIP                     0xA200B0
+#define CNVI_AUX_MISC_CHIP_MAC_STEP(_val)      (((_val) & 0xf000000) >> 24)
+#define CNVI_AUX_MISC_CHIP_PROD_TYPE(_val)     ((_val) & 0xfff)
+#define CNVI_AUX_MISC_CHIP_PROD_TYPE_BZ_U      0x930
+
 #define CNVR_AUX_MISC_CHIP                             0xA2B800
 #define CNVR_SCU_SD_REGS_SD_REG_DIG_DCDC_VTRIM         0xA29890
 #define CNVR_SCU_SD_REGS_SD_REG_ACTIVE_VDIG_MIRROR     0xA29938
index fa4a145..c8fc8b4 100644 (file)
@@ -119,7 +119,7 @@ int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans,
 
        prph_sc_ctrl->version.version = 0;
        prph_sc_ctrl->version.mac_id =
-               cpu_to_le16((u16)iwl_read32(trans, CSR_HW_REV));
+               cpu_to_le16((u16)trans->hw_rev);
        prph_sc_ctrl->version.size = cpu_to_le16(sizeof(*prph_scratch) / 4);
 
        control_flags |= IWL_PRPH_SCRATCH_MTR_MODE;
index 5f55efe..0fa9270 100644 (file)
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
 /*
  * Copyright (C) 2017 Intel Deutschland GmbH
- * Copyright (C) 2018-2022 Intel Corporation
+ * Copyright (C) 2018-2023 Intel Corporation
  */
 #include "iwl-trans.h"
 #include "iwl-fh.h"
@@ -180,7 +180,7 @@ int iwl_pcie_ctxt_info_init(struct iwl_trans *trans,
 
        ctxt_info->version.version = 0;
        ctxt_info->version.mac_id =
-               cpu_to_le16((u16)iwl_read32(trans, CSR_HW_REV));
+               cpu_to_le16((u16)trans->hw_rev);
        /* size is in DWs */
        ctxt_info->version.size = cpu_to_le16(sizeof(*ctxt_info) / 4);
 
index bbc8dc3..1ed67b7 100644 (file)
@@ -1155,6 +1155,20 @@ static void get_crf_id(struct iwl_trans *iwl_trans)
        iwl_trans->hw_cnv_id =
                iwl_read_prph_no_grab(iwl_trans, CNVI_AUX_MISC_CHIP);
 
+       /* In BZ, the MAC step must be read from the CNVI aux register */
+       if (CSR_HW_REV_TYPE(iwl_trans->hw_rev) == IWL_CFG_MAC_TYPE_BZ) {
+               u8 step = CNVI_AUX_MISC_CHIP_MAC_STEP(iwl_trans->hw_cnv_id);
+
+               /* For BZ-U, take B step also when A step is indicated */
+               if ((CNVI_AUX_MISC_CHIP_PROD_TYPE(iwl_trans->hw_cnv_id) ==
+                   CNVI_AUX_MISC_CHIP_PROD_TYPE_BZ_U) &&
+                   step == SILICON_A_STEP)
+                       step = SILICON_B_STEP;
+
+               iwl_trans->hw_rev_step = step;
+               iwl_trans->hw_rev |= step;
+       }
+
        /* Read cdb info (also contains the jacket info if needed in the future */
        iwl_trans->hw_wfpm_id =
                iwl_read_umac_prph_no_grab(iwl_trans, WFPM_OTP_CFG1_ADDR);