clk: sunxi-ng: sun6i: Export video PLLs
authorChen-Yu Tsai <wens@csie.org>
Fri, 29 Sep 2017 08:22:53 +0000 (16:22 +0800)
committerMaxime Ripard <maxime.ripard@free-electrons.com>
Fri, 29 Sep 2017 08:46:10 +0000 (10:46 +0200)
The 2x outputs of the 2 video PLL clocks are directly used by the
HDMI controller block.

Export them so they can be referenced in the device tree.

Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
drivers/clk/sunxi-ng/ccu-sun6i-a31.h
include/dt-bindings/clock/sun6i-a31-ccu.h

index 4e43401..27e6ad4 100644 (file)
@@ -27,7 +27,9 @@
 #define CLK_PLL_AUDIO_4X       4
 #define CLK_PLL_AUDIO_8X       5
 #define CLK_PLL_VIDEO0         6
-#define CLK_PLL_VIDEO0_2X      7
+
+/* The PLL_VIDEO0_2X clock is exported */
+
 #define CLK_PLL_VE             8
 #define CLK_PLL_DDR            9
 
@@ -35,7 +37,9 @@
 
 #define CLK_PLL_PERIPH_2X      11
 #define CLK_PLL_VIDEO1         12
-#define CLK_PLL_VIDEO1_2X      13
+
+/* The PLL_VIDEO1_2X clock is exported */
+
 #define CLK_PLL_GPU            14
 #define CLK_PLL_MIPI           15
 #define CLK_PLL9               16
index 4482530..c5d1334 100644 (file)
 #ifndef _DT_BINDINGS_CLK_SUN6I_A31_H_
 #define _DT_BINDINGS_CLK_SUN6I_A31_H_
 
+#define CLK_PLL_VIDEO0_2X      7
+
 #define CLK_PLL_PERIPH         10
 
+#define CLK_PLL_VIDEO1_2X      13
+
 #define CLK_CPU                        18
 
 #define CLK_AHB1_MIPIDSI       23