drm/i915/gvt: Change flood gvt dmesg into trace

Currently gvt dmesg is so heavy at drm.debug=0x2 that guest and
host almost couldn't run on xengt.

This patch transfer these repeated messages into trace, so dmesg
is light at drm.debug=0x2, and user could get the target message through
trace event and trace filter.

Suggested-by: Zhi Wang <zhi.a.wang@intel.com>
Signed-off-by: Xiong Zhang <xiong.y.zhang@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>

diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index 0b2a4a1..d3b4d42 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -472,6 +472,7 @@ enum {
        GVT_FAILSAFE_INSUFFICIENT_RESOURCE,
 };
 
+#include "trace.h"
 #include "mpt.h"
 
 #endif

diff --git a/drivers/gpu/drm/i915/gvt/interrupt.c b/drivers/gpu/drm/i915/gvt/interrupt.c
index 9d6812f..7a041b3 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/interrupt.c
+++ b/drivers/gpu/drm/i915/gvt/interrupt.c
@@ -31,6 +31,7 @@
 
 #include "i915_drv.h"
 #include "gvt.h"
+#include "trace.h"
 
 /* common offset among interrupt control registers */
 #define regbase_to_isr(base)   (base)
@@ -178,8 +179,8 @@ int intel_vgpu_reg_imr_handler(struct intel_vgpu *vgpu,
        struct intel_gvt_irq_ops *ops = gvt->irq.ops;
        u32 imr = *(u32 *)p_data;
 
-       gvt_dbg_irq("write IMR %x, new %08x, old %08x, changed %08x\n",
-                   reg, imr, vgpu_vreg(vgpu, reg), vgpu_vreg(vgpu, reg) ^ imr);
+       trace_write_ir(vgpu->id, "IMR", reg, imr, vgpu_vreg(vgpu, reg),
+                      (vgpu_vreg(vgpu, reg) ^ imr));
 
        vgpu_vreg(vgpu, reg) = imr;
 
@@ -209,8 +210,8 @@ int intel_vgpu_reg_master_irq_handler(struct intel_vgpu *vgpu,
        u32 ier = *(u32 *)p_data;
        u32 virtual_ier = vgpu_vreg(vgpu, reg);
 
-       gvt_dbg_irq("write MASTER_IRQ %x, new %08x, old %08x, changed %08x\n",
-                   reg, ier, virtual_ier, virtual_ier ^ ier);
+       trace_write_ir(vgpu->id, "MASTER_IRQ", reg, ier, virtual_ier,
+                      (virtual_ier ^ ier));
 
        /*
         * GEN8_MASTER_IRQ is a special irq register,
@@ -248,8 +249,8 @@ int intel_vgpu_reg_ier_handler(struct intel_vgpu *vgpu,
        struct intel_gvt_irq_info *info;
        u32 ier = *(u32 *)p_data;
 
-       gvt_dbg_irq("write IER %x, new %08x, old %08x, changed %08x\n",
-                   reg, ier, vgpu_vreg(vgpu, reg), vgpu_vreg(vgpu, reg) ^ ier);
+       trace_write_ir(vgpu->id, "IER", reg, ier, vgpu_vreg(vgpu, reg),
+                      (vgpu_vreg(vgpu, reg) ^ ier));
 
        vgpu_vreg(vgpu, reg) = ier;
 
@@ -285,8 +286,8 @@ int intel_vgpu_reg_iir_handler(struct intel_vgpu *vgpu, unsigned int reg,
                iir_to_regbase(reg));
        u32 iir = *(u32 *)p_data;
 
-       gvt_dbg_irq("write IIR %x, new %08x, old %08x, changed %08x\n",
-                   reg, iir, vgpu_vreg(vgpu, reg), vgpu_vreg(vgpu, reg) ^ iir);
+       trace_write_ir(vgpu->id, "IIR", reg, iir, vgpu_vreg(vgpu, reg),
+                      (vgpu_vreg(vgpu, reg) ^ iir));
 
        if (WARN_ON(!info))
                return -EINVAL;
@@ -411,8 +412,7 @@ static void propagate_event(struct intel_gvt_irq *irq,
 
        if (!test_bit(bit, (void *)&vgpu_vreg(vgpu,
                                        regbase_to_imr(reg_base)))) {
-               gvt_dbg_irq("set bit (%d) for (%s) for vgpu (%d)\n",
-                               bit, irq_name[event], vgpu->id);
+               trace_propagate_event(vgpu->id, irq_name[event], bit);
                set_bit(bit, (void *)&vgpu_vreg(vgpu,
                                        regbase_to_iir(reg_base)));
        }

diff --git a/drivers/gpu/drm/i915/gvt/mpt.h b/drivers/gpu/drm/i915/gvt/mpt.h
index 4193536..f0e5487 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/mpt.h
+++ b/drivers/gpu/drm/i915/gvt/mpt.h
@@ -133,8 +133,7 @@ static inline int intel_gvt_hypervisor_inject_msi(struct intel_vgpu *vgpu)
        if (WARN(control & GENMASK(15, 1), "only support one MSI format\n"))
                return -EINVAL;
 
-       gvt_dbg_irq("vgpu%d: inject msi address %x data%x\n", vgpu->id, addr,
-                   data);
+       trace_inject_msi(vgpu->id, addr, data);
 
        ret = intel_gvt_host.mpt->inject_msi(vgpu->handle, addr, data);
        if (ret)

diff --git a/drivers/gpu/drm/i915/gvt/render.c b/drivers/gpu/drm/i915/gvt/render.c
index 19d98c9..28c9118 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/render.c
+++ b/drivers/gpu/drm/i915/gvt/render.c
@@ -35,6 +35,7 @@
 
 #include "i915_drv.h"
 #include "gvt.h"
+#include "trace.h"
 
 struct render_mmio {
        int ring_id;
@@ -306,9 +307,9 @@ static void switch_mmio_to_vgpu(struct intel_vgpu *vgpu, int ring_id)
                I915_WRITE(mmio->reg, v);
                POSTING_READ(mmio->reg);
 
-               gvt_dbg_render("load reg %x old %x new %x\n",
-                               i915_mmio_reg_offset(mmio->reg),
-                               mmio->value, v);
+               trace_render_mmio(vgpu->id, "load",
+                                 i915_mmio_reg_offset(mmio->reg),
+                                 mmio->value, v);
        }
        handle_tlb_pending_event(vgpu, ring_id);
 }
@@ -345,9 +346,9 @@ static void switch_mmio_to_host(struct intel_vgpu *vgpu, int ring_id)
                I915_WRITE(mmio->reg, v);
                POSTING_READ(mmio->reg);
 
-               gvt_dbg_render("restore reg %x old %x new %x\n",
-                               i915_mmio_reg_offset(mmio->reg),
-                               mmio->value, v);
+               trace_render_mmio(vgpu->id, "restore",
+                                 i915_mmio_reg_offset(mmio->reg),
+                                 mmio->value, v);
        }
 }
 

diff --git a/drivers/gpu/drm/i915/gvt/trace.h b/drivers/gpu/drm/i915/gvt/trace.h
index 9171291..8c15038 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/trace.h
+++ b/drivers/gpu/drm/i915/gvt/trace.h
@@ -256,6 +256,106 @@ TRACE_EVENT(gvt_command,
                __entry->ip_gma,
                __print_array(__get_dynamic_array(raw_cmd), __entry->cmd_len, 4))
 );
+
+#define GVT_TEMP_STR_LEN 10
+TRACE_EVENT(write_ir,
+       TP_PROTO(int id, char *reg_name, unsigned int reg, unsigned int new_val,
+                unsigned int old_val, bool changed),
+
+       TP_ARGS(id, reg_name, reg, new_val, old_val, changed),
+
+       TP_STRUCT__entry(
+               __field(int, id)
+               __array(char, buf, GVT_TEMP_STR_LEN)
+               __field(unsigned int, reg)
+               __field(unsigned int, new_val)
+               __field(unsigned int, old_val)
+               __field(bool, changed)
+       ),
+
+       TP_fast_assign(
+               __entry->id = id;
+               snprintf(__entry->buf, GVT_TEMP_STR_LEN, "%s", reg_name);
+               __entry->reg = reg;
+               __entry->new_val = new_val;
+               __entry->old_val = old_val;
+               __entry->changed = changed;
+       ),
+
+       TP_printk("VM%u write [%s] %x, new %08x, old %08x, changed %08x\n",
+                 __entry->id, __entry->buf, __entry->reg, __entry->new_val,
+                 __entry->old_val, __entry->changed)
+);
+
+TRACE_EVENT(propagate_event,
+       TP_PROTO(int id, const char *irq_name, int bit),
+
+       TP_ARGS(id, irq_name, bit),
+
+       TP_STRUCT__entry(
+               __field(int, id)
+               __array(char, buf, GVT_TEMP_STR_LEN)
+               __field(int, bit)
+       ),
+
+       TP_fast_assign(
+               __entry->id = id;
+               snprintf(__entry->buf, GVT_TEMP_STR_LEN, "%s", irq_name);
+               __entry->bit = bit;
+       ),
+
+       TP_printk("Set bit (%d) for (%s) for vgpu (%d)\n",
+                 __entry->bit, __entry->buf, __entry->id)
+);
+
+TRACE_EVENT(inject_msi,
+       TP_PROTO(int id, unsigned int address, unsigned int data),
+
+       TP_ARGS(id, address, data),
+
+       TP_STRUCT__entry(
+               __field(int, id)
+               __field(unsigned int, address)
+               __field(unsigned int, data)
+       ),
+
+       TP_fast_assign(
+               __entry->id = id;
+               __entry->address = address;
+               __entry->data = data;
+       ),
+
+       TP_printk("vgpu%d:inject msi address %x data %x\n",
+                 __entry->id, __entry->address, __entry->data)
+);
+
+TRACE_EVENT(render_mmio,
+       TP_PROTO(int id, char *action, unsigned int reg,
+                unsigned int old_val, unsigned int new_val),
+
+       TP_ARGS(id, action, reg, new_val, old_val),
+
+       TP_STRUCT__entry(
+               __field(int, id)
+               __array(char, buf, GVT_TEMP_STR_LEN)
+               __field(unsigned int, reg)
+               __field(unsigned int, old_val)
+               __field(unsigned int, new_val)
+       ),
+
+       TP_fast_assign(
+               __entry->id = id;
+               snprintf(__entry->buf, GVT_TEMP_STR_LEN, "%s", action);
+               __entry->reg = reg;
+               __entry->old_val = old_val;
+               __entry->new_val = new_val;
+       ),
+
+       TP_printk("VM%u %s reg %x, old %08x new %08x\n",
+                 __entry->id, __entry->buf, __entry->reg,
+                 __entry->old_val, __entry->new_val)
+);
+
 #endif /* _GVT_TRACE_H_ */
 
 /* This part must be out of protection */