drm: pl111: Absorb the external register header

The PL111 DRM driver is now the sole user of the external
CLCD registers header file, so let's absorb that into the
pl111_drm.h file and save the external include.

Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Cc: Russell King <linux@armlinux.org.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20200609200446.153209-3-linus.walleij@linaro.org

diff --git a/drivers/gpu/drm/pl111/pl111_debugfs.c b/drivers/gpu/drm/pl111/pl111_debugfs.c
index 26ca8cd..317f68a 100644 (file)
--- a/drivers/gpu/drm/pl111/pl111_debugfs.c
+++ b/drivers/gpu/drm/pl111/pl111_debugfs.c
@@ -3,7 +3,6 @@
  *  Copyright © 2017 Broadcom
  */
 
-#include <linux/amba/clcd-regs.h>
 #include <linux/seq_file.h>
 
 #include <drm/drm_debugfs.h>

diff --git a/drivers/gpu/drm/pl111/pl111_display.c b/drivers/gpu/drm/pl111/pl111_display.c
index 703ddc8..b3e8697 100644 (file)
--- a/drivers/gpu/drm/pl111/pl111_display.c
+++ b/drivers/gpu/drm/pl111/pl111_display.c
@@ -9,7 +9,6 @@
  * Copyright (C) 2011 Texas Instruments
  */
 
-#include <linux/amba/clcd-regs.h>
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/version.h>

diff --git a/drivers/gpu/drm/pl111/pl111_drm.h b/drivers/gpu/drm/pl111/pl111_drm.h
index ba399bc..2a46b5b 100644 (file)
--- a/drivers/gpu/drm/pl111/pl111_drm.h
+++ b/drivers/gpu/drm/pl111/pl111_drm.h
@@ -23,6 +23,79 @@
 #include <drm/drm_panel.h>
 #include <drm/drm_simple_kms_helper.h>
 
+/*
+ * CLCD Controller Internal Register addresses
+ */
+#define CLCD_TIM0              0x00000000
+#define CLCD_TIM1              0x00000004
+#define CLCD_TIM2              0x00000008
+#define CLCD_TIM3              0x0000000c
+#define CLCD_UBAS              0x00000010
+#define CLCD_LBAS              0x00000014
+
+#define CLCD_PL110_IENB                0x00000018
+#define CLCD_PL110_CNTL                0x0000001c
+#define CLCD_PL110_STAT                0x00000020
+#define CLCD_PL110_INTR                0x00000024
+#define CLCD_PL110_UCUR                0x00000028
+#define CLCD_PL110_LCUR                0x0000002C
+
+#define CLCD_PL111_CNTL                0x00000018
+#define CLCD_PL111_IENB                0x0000001c
+#define CLCD_PL111_RIS         0x00000020
+#define CLCD_PL111_MIS         0x00000024
+#define CLCD_PL111_ICR         0x00000028
+#define CLCD_PL111_UCUR                0x0000002c
+#define CLCD_PL111_LCUR                0x00000030
+
+#define CLCD_PALL              0x00000200
+#define CLCD_PALETTE           0x00000200
+
+#define TIM2_PCD_LO_MASK       GENMASK(4, 0)
+#define TIM2_PCD_LO_BITS       5
+#define TIM2_CLKSEL            (1 << 5)
+#define TIM2_ACB_MASK          GENMASK(10, 6)
+#define TIM2_IVS               (1 << 11)
+#define TIM2_IHS               (1 << 12)
+#define TIM2_IPC               (1 << 13)
+#define TIM2_IOE               (1 << 14)
+#define TIM2_BCD               (1 << 26)
+#define TIM2_PCD_HI_MASK       GENMASK(31, 27)
+#define TIM2_PCD_HI_BITS       5
+#define TIM2_PCD_HI_SHIFT      27
+
+#define CNTL_LCDEN             (1 << 0)
+#define CNTL_LCDBPP1           (0 << 1)
+#define CNTL_LCDBPP2           (1 << 1)
+#define CNTL_LCDBPP4           (2 << 1)
+#define CNTL_LCDBPP8           (3 << 1)
+#define CNTL_LCDBPP16          (4 << 1)
+#define CNTL_LCDBPP16_565      (6 << 1)
+#define CNTL_LCDBPP16_444      (7 << 1)
+#define CNTL_LCDBPP24          (5 << 1)
+#define CNTL_LCDBW             (1 << 4)
+#define CNTL_LCDTFT            (1 << 5)
+#define CNTL_LCDMONO8          (1 << 6)
+#define CNTL_LCDDUAL           (1 << 7)
+#define CNTL_BGR               (1 << 8)
+#define CNTL_BEBO              (1 << 9)
+#define CNTL_BEPO              (1 << 10)
+#define CNTL_LCDPWR            (1 << 11)
+#define CNTL_LCDVCOMP(x)       ((x) << 12)
+#define CNTL_LDMAFIFOTIME      (1 << 15)
+#define CNTL_WATERMARK         (1 << 16)
+
+/* ST Microelectronics variant bits */
+#define CNTL_ST_1XBPP_444      0x0
+#define CNTL_ST_1XBPP_5551     (1 << 17)
+#define CNTL_ST_1XBPP_565      (1 << 18)
+#define CNTL_ST_CDWID_12       0x0
+#define CNTL_ST_CDWID_16       (1 << 19)
+#define CNTL_ST_CDWID_18       (1 << 20)
+#define CNTL_ST_CDWID_24       ((1 << 19) | (1 << 20))
+#define CNTL_ST_CEAEN          (1 << 21)
+#define CNTL_ST_LCDBPP24_PACKED        (6 << 1)
+
 #define CLCD_IRQ_NEXTBASE_UPDATE BIT(2)
 
 struct drm_minor;

diff --git a/drivers/gpu/drm/pl111/pl111_drv.c b/drivers/gpu/drm/pl111/pl111_drv.c
index da0c39d..96e58fd 100644 (file)
--- a/drivers/gpu/drm/pl111/pl111_drv.c
+++ b/drivers/gpu/drm/pl111/pl111_drv.c
@@ -47,7 +47,6 @@
  */
 
 #include <linux/amba/bus.h>
-#include <linux/amba/clcd-regs.h>
 #include <linux/dma-buf.h>
 #include <linux/module.h>
 #include <linux/of.h>

diff --git a/drivers/gpu/drm/pl111/pl111_versatile.c b/drivers/gpu/drm/pl111/pl111_versatile.c
index 1127082..bdd883f 100644 (file)
--- a/drivers/gpu/drm/pl111/pl111_versatile.c
+++ b/drivers/gpu/drm/pl111/pl111_versatile.c
@@ -9,7 +9,6 @@
  * Major contributions and discoveries by Russell King.
  */
 
-#include <linux/amba/clcd-regs.h>
 #include <linux/bitops.h>
 #include <linux/device.h>
 #include <linux/mfd/syscon.h>

diff --git a/include/linux/amba/clcd-regs.h b/include/linux/amba/clcd-regs.h
deleted file mode 100644 (file)
index 421b0fa..0000000
--- a/include/linux/amba/clcd-regs.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * David A Rusling
- *
- * Copyright (C) 2001 ARM Limited
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file COPYING in the main directory of this archive
- * for more details.
- */
-
-#ifndef AMBA_CLCD_REGS_H
-#define AMBA_CLCD_REGS_H
-
-/*
- * CLCD Controller Internal Register addresses
- */
-#define CLCD_TIM0              0x00000000
-#define CLCD_TIM1              0x00000004
-#define CLCD_TIM2              0x00000008
-#define CLCD_TIM3              0x0000000c
-#define CLCD_UBAS              0x00000010
-#define CLCD_LBAS              0x00000014
-
-#define CLCD_PL110_IENB                0x00000018
-#define CLCD_PL110_CNTL                0x0000001c
-#define CLCD_PL110_STAT                0x00000020
-#define CLCD_PL110_INTR        0x00000024
-#define CLCD_PL110_UCUR                0x00000028
-#define CLCD_PL110_LCUR                0x0000002C
-
-#define CLCD_PL111_CNTL                0x00000018
-#define CLCD_PL111_IENB                0x0000001c
-#define CLCD_PL111_RIS         0x00000020
-#define CLCD_PL111_MIS         0x00000024
-#define CLCD_PL111_ICR         0x00000028
-#define CLCD_PL111_UCUR                0x0000002c
-#define CLCD_PL111_LCUR                0x00000030
-
-#define CLCD_PALL              0x00000200
-#define CLCD_PALETTE           0x00000200
-
-#define TIM2_PCD_LO_MASK       GENMASK(4, 0)
-#define TIM2_PCD_LO_BITS       5
-#define TIM2_CLKSEL            (1 << 5)
-#define TIM2_ACB_MASK          GENMASK(10, 6)
-#define TIM2_IVS               (1 << 11)
-#define TIM2_IHS               (1 << 12)
-#define TIM2_IPC               (1 << 13)
-#define TIM2_IOE               (1 << 14)
-#define TIM2_BCD               (1 << 26)
-#define TIM2_PCD_HI_MASK       GENMASK(31, 27)
-#define TIM2_PCD_HI_BITS       5
-#define TIM2_PCD_HI_SHIFT      27
-
-#define CNTL_LCDEN             (1 << 0)
-#define CNTL_LCDBPP1           (0 << 1)
-#define CNTL_LCDBPP2           (1 << 1)
-#define CNTL_LCDBPP4           (2 << 1)
-#define CNTL_LCDBPP8           (3 << 1)
-#define CNTL_LCDBPP16          (4 << 1)
-#define CNTL_LCDBPP16_565      (6 << 1)
-#define CNTL_LCDBPP16_444      (7 << 1)
-#define CNTL_LCDBPP24          (5 << 1)
-#define CNTL_LCDBW             (1 << 4)
-#define CNTL_LCDTFT            (1 << 5)
-#define CNTL_LCDMONO8          (1 << 6)
-#define CNTL_LCDDUAL           (1 << 7)
-#define CNTL_BGR               (1 << 8)
-#define CNTL_BEBO              (1 << 9)
-#define CNTL_BEPO              (1 << 10)
-#define CNTL_LCDPWR            (1 << 11)
-#define CNTL_LCDVCOMP(x)       ((x) << 12)
-#define CNTL_LDMAFIFOTIME      (1 << 15)
-#define CNTL_WATERMARK         (1 << 16)
-
-/* ST Microelectronics variant bits */
-#define CNTL_ST_1XBPP_444      0x0
-#define CNTL_ST_1XBPP_5551     (1 << 17)
-#define CNTL_ST_1XBPP_565      (1 << 18)
-#define CNTL_ST_CDWID_12       0x0
-#define CNTL_ST_CDWID_16       (1 << 19)
-#define CNTL_ST_CDWID_18       (1 << 20)
-#define CNTL_ST_CDWID_24       ((1 << 19)|(1 << 20))
-#define CNTL_ST_CEAEN          (1 << 21)
-#define CNTL_ST_LCDBPP24_PACKED        (6 << 1)
-
-#endif /* AMBA_CLCD_REGS_H */