drm/i915/adl-n: Enable ADL-N platform
authorTejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
Fri, 10 Dec 2021 05:18:02 +0000 (10:48 +0530)
committerJani Nikula <jani.nikula@intel.com>
Mon, 20 Dec 2021 13:42:33 +0000 (15:42 +0200)
Adding PCI device ids and enabling ADL-N platform.
ADL-N from i915 point of view is subplatform of ADL-P.

BSpec: 68397

Changes since V2:
- Added version log history
Changes since V1:
- replace IS_ALDERLAKE_N with IS_ADLP_N - Jani Nikula

Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211210051802.4063958-1-tejaskumarx.surendrakumar.upadhyay@intel.com
arch/x86/kernel/early-quirks.c
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/i915_pci.c
drivers/gpu/drm/i915/intel_device_info.c
drivers/gpu/drm/i915/intel_device_info.h
include/drm/i915_pciids.h

index fd2d3ab..1ca3a56 100644 (file)
@@ -554,6 +554,7 @@ static const struct pci_device_id intel_early_ids[] __initconst = {
        INTEL_RKL_IDS(&gen11_early_ops),
        INTEL_ADLS_IDS(&gen11_early_ops),
        INTEL_ADLP_IDS(&gen11_early_ops),
+       INTEL_ADLN_IDS(&gen11_early_ops),
        INTEL_RPLS_IDS(&gen11_early_ops),
 };
 
index 23e2a1b..b7d6402 100644 (file)
@@ -1267,6 +1267,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
        IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
 #define IS_ADLS_RPLS(dev_priv) \
        IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL_S)
+#define IS_ADLP_N(dev_priv) \
+       IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
                                    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
 #define IS_BDW_ULT(dev_priv) \
index 12e331f..960c358 100644 (file)
@@ -1129,6 +1129,7 @@ static const struct pci_device_id pciidlist[] = {
        INTEL_RKL_IDS(&rkl_info),
        INTEL_ADLS_IDS(&adl_s_info),
        INTEL_ADLP_IDS(&adl_p_info),
+       INTEL_ADLN_IDS(&adl_p_info),
        INTEL_DG1_IDS(&dg1_info),
        INTEL_RPLS_IDS(&adl_s_info),
        {0, 0, 0}
index bb7d37b..24e05f1 100644 (file)
@@ -177,6 +177,10 @@ static const u16 subplatform_portf_ids[] = {
        INTEL_ICL_PORT_F_IDS(0),
 };
 
+static const u16 subplatform_n_ids[] = {
+       INTEL_ADLN_IDS(0),
+};
+
 static const u16 subplatform_rpls_ids[] = {
        INTEL_RPLS_IDS(0),
 };
@@ -217,6 +221,9 @@ void intel_device_info_subplatform_init(struct drm_i915_private *i915)
        } else if (find_devid(devid, subplatform_portf_ids,
                              ARRAY_SIZE(subplatform_portf_ids))) {
                mask = BIT(INTEL_SUBPLATFORM_PORTF);
+       } else if (find_devid(devid, subplatform_n_ids,
+                               ARRAY_SIZE(subplatform_n_ids))) {
+               mask = BIT(INTEL_SUBPLATFORM_N);
        } else if (find_devid(devid, subplatform_rpls_ids,
                              ARRAY_SIZE(subplatform_rpls_ids))) {
                mask = BIT(INTEL_SUBPLATFORM_RPL_S);
index 7cef02f..2a4e32b 100644 (file)
@@ -113,6 +113,9 @@ enum intel_platform {
 /* ADL-S */
 #define INTEL_SUBPLATFORM_RPL_S        0
 
+/* ADL-P */
+#define INTEL_SUBPLATFORM_N    0
+
 enum intel_ppgtt_type {
        INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
        INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
index baf3d1d..533890d 100644 (file)
        INTEL_VGA_DEVICE(0x46C2, info), \
        INTEL_VGA_DEVICE(0x46C3, info)
 
+/* ADL-N */
+#define INTEL_ADLN_IDS(info) \
+       INTEL_VGA_DEVICE(0x46D0, info), \
+       INTEL_VGA_DEVICE(0x46D1, info), \
+       INTEL_VGA_DEVICE(0x46D2, info)
+
 /* RPL-S */
 #define INTEL_RPLS_IDS(info) \
        INTEL_VGA_DEVICE(0xA780, info), \