drm/i915/adl_s: Add adl-s ddc pin mapping
authorAditya Swarup <aditya.swarup@intel.com>
Mon, 25 Jan 2021 14:07:51 +0000 (06:07 -0800)
committerLucas De Marchi <lucas.demarchi@intel.com>
Tue, 26 Jan 2021 15:10:45 +0000 (07:10 -0800)
ADL-S requires TC pins to set up ddc for Combo PHY B, C, D and E.
Combo PHY A still uses the old ddc pin mapping.

From VBT, ddc pin info suggests the following mapping:
VBT                 DRIVER
DDI B->ddc_pin=2 should translate to PORT_D->0x9
DDI C->ddc_pin=3 should translate to PORT_E->0xa
DDI D->ddc_pin=4 should translate to PORT_F->0xb
DDI E->ddc_pin=5 should translate to PORT_G->0xc

Adding pin map to facilitate this translation as we cannot use existing
icl ddc pin map due to conflict with DDI B and DDI C info.

Bspec:20124

v2: Replace IS_ALDERLAKE_S() with HAS_PCH_ADP() as the pin map pairing
depends on the PCH being used rather than the platform.(mdroper)

v3:
- Modify adls_port_to_ddc_pin() to make PHY_A the special case for
  check, else return pin mapping based on correct arithmetic with phy
  offset. Remove redundant platform checks and use HAS_PCH_ADP() instead
  of IS_ALDERLAKE_S() in intel_hdmi_ddc_pin().(mdroper)

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210125140753.347998-9-aditya.swarup@intel.com
drivers/gpu/drm/i915/display/intel_bios.c
drivers/gpu/drm/i915/display/intel_hdmi.c
drivers/gpu/drm/i915/display/intel_vbt_defs.h

index 987cf50..e575e58 100644 (file)
@@ -1630,12 +1630,23 @@ static const u8 rkl_pch_tgp_ddc_pin_map[] = {
        [RKL_DDC_BUS_DDI_E] = GMBUS_PIN_10_TC2_ICP,
 };
 
+static const u8 adls_ddc_pin_map[] = {
+       [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT,
+       [ADLS_DDC_BUS_PORT_TC1] = GMBUS_PIN_9_TC1_ICP,
+       [ADLS_DDC_BUS_PORT_TC2] = GMBUS_PIN_10_TC2_ICP,
+       [ADLS_DDC_BUS_PORT_TC3] = GMBUS_PIN_11_TC3_ICP,
+       [ADLS_DDC_BUS_PORT_TC4] = GMBUS_PIN_12_TC4_ICP,
+};
+
 static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
 {
        const u8 *ddc_pin_map;
        int n_entries;
 
-       if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) {
+       if (HAS_PCH_ADP(dev_priv)) {
+               ddc_pin_map = adls_ddc_pin_map;
+               n_entries = ARRAY_SIZE(adls_ddc_pin_map);
+       } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) {
                return vbt_pin;
        } else if (IS_ROCKETLAKE(dev_priv) && INTEL_PCH_TYPE(dev_priv) == PCH_TGP) {
                ddc_pin_map = rkl_pch_tgp_ddc_pin_map;
index c595959..0fe9094 100644 (file)
@@ -3135,6 +3135,22 @@ static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
        return intel_port_to_phy(dev_priv, port) + 1;
 }
 
+static u8 adls_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
+{
+       enum phy phy = intel_port_to_phy(dev_priv, port);
+
+       WARN_ON(port == PORT_B || port == PORT_C);
+
+       /*
+        * Pin mapping for ADL-S requires TC pins for all combo phy outputs
+        * except first combo output.
+        */
+       if (phy == PHY_A)
+               return GMBUS_PIN_1_BXT;
+
+       return GMBUS_PIN_9_TC1_ICP + phy - PHY_B;
+}
+
 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
                              enum port port)
 {
@@ -3172,7 +3188,9 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
                return ddc_pin;
        }
 
-       if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+       if (HAS_PCH_ADP(dev_priv))
+               ddc_pin = adls_port_to_ddc_pin(dev_priv, port);
+       else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
                ddc_pin = dg1_port_to_ddc_pin(dev_priv, port);
        else if (IS_ROCKETLAKE(dev_priv))
                ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
index 187ec57..6d10fa0 100644 (file)
@@ -327,6 +327,10 @@ enum vbt_gmbus_ddi {
        ICL_DDC_BUS_PORT_4,
        TGL_DDC_BUS_PORT_5,
        TGL_DDC_BUS_PORT_6,
+       ADLS_DDC_BUS_PORT_TC1 = 0x2,
+       ADLS_DDC_BUS_PORT_TC2,
+       ADLS_DDC_BUS_PORT_TC3,
+       ADLS_DDC_BUS_PORT_TC4
 };
 
 #define DP_AUX_A 0x40