drm/amd/display: bypass post csc for additional color spaces in dal

[Why]
For RGB BT2020 full and limited color spaces, overlay adjustments were
applied twice (once by MM and once by DAL). This results in incorrect
colours and a noticeable difference between mpo and non-mpo cases.

[How]
Add RGB BT2020 full and limited color spaces to list that bypasses post
csc adjustment.

Reviewed-by: Aric Cyr <aric.cyr@amd.com>
Signed-off-by: Clay King <clayking@amd.com>
Signed-off-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
index ef4a161..c792353 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
@@ -376,10 +376,10 @@ void dpp3_cnv_setup (
 
                tbl_entry.color_space = input_color_space;
 
-               if (color_space >= COLOR_SPACE_YCBCR601)
-                       select = INPUT_CSC_SELECT_ICSC;
-               else
+               if (dpp3_should_bypass_post_csc_for_colorspace(color_space))
                        select = INPUT_CSC_SELECT_BYPASS;
+               else
+                       select = INPUT_CSC_SELECT_ICSC;
 
                dpp3_program_post_csc(dpp_base, color_space, select,
                                      &tbl_entry);
@@ -1541,3 +1541,18 @@ bool dpp3_construct(
        return true;
 }
 
+bool dpp3_should_bypass_post_csc_for_colorspace(enum dc_color_space dc_color_space)
+{
+       switch (dc_color_space) {
+       case COLOR_SPACE_UNKNOWN:
+       case COLOR_SPACE_SRGB:
+       case COLOR_SPACE_XR_RGB:
+       case COLOR_SPACE_SRGB_LIMITED:
+       case COLOR_SPACE_MSREF_SCRGB:
+       case COLOR_SPACE_2020_RGB_FULLRANGE:
+       case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
+               return true;
+       default:
+               return false;
+       }
+}

diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
index d4a70b4..6a61b99 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
@@ -644,4 +644,8 @@ void dpp3_program_cm_dealpha(
 
 void dpp3_cm_get_gamut_remap(struct dpp *dpp_base,
                             struct dpp_grph_csc_adjustment *adjust);
+
+bool dpp3_should_bypass_post_csc_for_colorspace(
+               enum dc_color_space dc_color_space);
+
 #endif /* __DC_HWSS_DCN30_H__ */

diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c
index 96c2c85..2d6a646 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c
@@ -206,10 +206,10 @@ void dpp401_dpp_setup(
 
                tbl_entry.color_space = input_color_space;
 
-               if (color_space >= COLOR_SPACE_YCBCR601)
-                       select = INPUT_CSC_SELECT_ICSC;
-               else
+               if (dpp3_should_bypass_post_csc_for_colorspace(color_space))
                        select = INPUT_CSC_SELECT_BYPASS;
+               else
+                       select = INPUT_CSC_SELECT_ICSC;
 
                dpp3_program_post_csc(dpp_base, color_space, select,
                        &tbl_entry);