drm/amd/display: Use meaningful size for block_sequence array

[Why]
This array was initially defined as size 50. There were array overflow
issues so the size was increased to 100. To ensure such issues are
avoided in the future, the size should be set based on the possible
contents instead of an arbitrary value.

[How]
 - upper bound, assume every update occurs on max number of pipes
 - define array sizes for function parameters, for static analysis

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
index 55b32df..7014b8d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
@@ -697,7 +697,7 @@ void get_fams2_visual_confirm_color(
 void hwss_build_fast_sequence(struct dc *dc,
                struct dc_dmub_cmd *dc_dmub_cmd,
                unsigned int dmub_cmd_count,
-               struct block_sequence block_sequence[],
+               struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE],
                unsigned int *num_steps,
                struct pipe_ctx *pipe_ctx,
                struct dc_stream_status *stream_status,
@@ -896,7 +896,7 @@ void hwss_build_fast_sequence(struct dc *dc,
 }
 
 void hwss_execute_sequence(struct dc *dc,
-               struct block_sequence block_sequence[],
+               struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE],
                int num_steps)
 {
        unsigned int i;

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
index c8b5ed8..3a07950 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
@@ -195,6 +195,8 @@ enum block_sequence_func {
        DMUB_SUBVP_SAVE_SURF_ADDR,
        HUBP_WAIT_FOR_DCC_META_PROP,
        DMUB_FAMS2_GLOBAL_CONTROL_LOCK_FAST,
+       /* This must be the last value in this enum, add new ones above */
+       HWSS_BLOCK_SEQUENCE_FUNC_COUNT
 };
 
 struct block_sequence {
@@ -202,6 +204,8 @@ struct block_sequence {
        enum block_sequence_func func;
 };
 
+#define MAX_HWSS_BLOCK_SEQUENCE_SIZE (HWSS_BLOCK_SEQUENCE_FUNC_COUNT * MAX_PIPES)
+
 struct hw_sequencer_funcs {
        void (*hardware_release)(struct dc *dc);
        /* Embedded Display Related */
@@ -534,13 +538,13 @@ void set_drr_and_clear_adjust_pending(
                struct drr_params *params);
 
 void hwss_execute_sequence(struct dc *dc,
-               struct block_sequence block_sequence[],
+               struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE],
                int num_steps);
 
 void hwss_build_fast_sequence(struct dc *dc,
                struct dc_dmub_cmd *dc_dmub_cmd,
                unsigned int dmub_cmd_count,
-               struct block_sequence block_sequence[],
+               struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE],
                unsigned int *num_steps,
                struct pipe_ctx *pipe_ctx,
                struct dc_stream_status *stream_status,

diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index c1c8742..338bc24 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -630,7 +630,7 @@ struct dc_state {
         */
        struct bw_context bw_ctx;
 
-       struct block_sequence block_sequence[100];
+       struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE];
        unsigned int block_sequence_steps;
        struct dc_dmub_cmd dc_dmub_cmd[10];
        unsigned int dmub_cmd_count;