net: macb: Fix SUBNS increment and increase resolution
authorHarini Katakam <harini.katakam@xilinx.com>
Thu, 27 Jun 2019 06:21:00 +0000 (11:51 +0530)
committerDavid S. Miller <davem@davemloft.net>
Sat, 29 Jun 2019 18:09:18 +0000 (11:09 -0700)
The subns increment register has 24 bits as follows:
RegBit[15:0] = Subns[23:8]; RegBit[31:24] = Subns[7:0]

Fix the same in the driver and increase sub ns resolution to the
best capable, 24 bits. This should be the case on all GEM versions
that this PTP driver supports.

Signed-off-by: Harini Katakam <harini.katakam@xilinx.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/cadence/macb.h
drivers/net/ethernet/cadence/macb_ptp.c

index b3b2a00..9873558 100644 (file)
 
 /* Bitfields in TISUBN */
 #define GEM_SUBNSINCR_OFFSET                   0
-#define GEM_SUBNSINCR_SIZE                     16
+#define GEM_SUBNSINCRL_OFFSET                  24
+#define GEM_SUBNSINCRL_SIZE                    8
+#define GEM_SUBNSINCRH_OFFSET                  0
+#define GEM_SUBNSINCRH_SIZE                    16
+#define GEM_SUBNSINCR_SIZE                     24
 
 /* Bitfields in TI */
 #define GEM_NSINCR_OFFSET                      0
index 6276eac..43a3f0d 100644 (file)
@@ -104,7 +104,10 @@ static int gem_tsu_incr_set(struct macb *bp, struct tsu_incr *incr_spec)
         * to take effect.
         */
        spin_lock_irqsave(&bp->tsu_clk_lock, flags);
-       gem_writel(bp, TISUBN, GEM_BF(SUBNSINCR, incr_spec->sub_ns));
+       /* RegBit[15:0] = Subns[23:8]; RegBit[31:24] = Subns[7:0] */
+       gem_writel(bp, TISUBN, GEM_BF(SUBNSINCRL, incr_spec->sub_ns) |
+                  GEM_BF(SUBNSINCRH, (incr_spec->sub_ns >>
+                         GEM_SUBNSINCRL_SIZE)));
        gem_writel(bp, TI, GEM_BF(NSINCR, incr_spec->ns));
        spin_unlock_irqrestore(&bp->tsu_clk_lock, flags);