drm/i915: pass dev_priv explicitly to TRANS_PSR_IIR

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the TRANS_PSR_IIR register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/3a03109d11e7f55a456c3e5ef28d3ffa69582d3d.1714471597.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index a9bcf24..c41f058 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -876,7 +876,8 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
                        struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 
                        if (DISPLAY_VER(dev_priv) >= 12)
-                               iir_reg = TRANS_PSR_IIR(intel_dp->psr.transcoder);
+                               iir_reg = TRANS_PSR_IIR(dev_priv,
+                                                       intel_dp->psr.transcoder);
                        else
                                iir_reg = EDP_PSR_IIR;
 
@@ -1458,7 +1459,9 @@ void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
                        intel_uncore_write(uncore,
                                           TRANS_PSR_IMR(dev_priv, trans),
                                           0xffffffff);
-                       intel_uncore_write(uncore, TRANS_PSR_IIR(trans), 0xffffffff);
+                       intel_uncore_write(uncore,
+                                          TRANS_PSR_IIR(dev_priv, trans),
+                                          0xffffffff);
                }
        } else {
                intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
@@ -1690,7 +1693,8 @@ void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
                        if (!intel_display_power_is_enabled(dev_priv, domain))
                                continue;
 
-                       gen3_assert_iir_is_zero(uncore, TRANS_PSR_IIR(trans));
+                       gen3_assert_iir_is_zero(uncore,
+                                               TRANS_PSR_IIR(dev_priv, trans));
                }
        } else {
                gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 12b541e..0b1f7e6 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -314,7 +314,7 @@ static i915_reg_t psr_iir_reg(struct drm_i915_private *dev_priv,
                              enum transcoder cpu_transcoder)
 {
        if (DISPLAY_VER(dev_priv) >= 12)
-               return TRANS_PSR_IIR(cpu_transcoder);
+               return TRANS_PSR_IIR(dev_priv, cpu_transcoder);
        else
                return EDP_PSR_IIR;
 }

diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index 40dc6ee..5fd4f87 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -67,7 +67,7 @@
 #define _PSR_IMR_A                             0x60814
 #define _PSR_IIR_A                             0x60818
 #define TRANS_PSR_IMR(dev_priv, tran)                  _MMIO_TRANS2(dev_priv, tran, _PSR_IMR_A)
-#define TRANS_PSR_IIR(tran)                    _MMIO_TRANS2(dev_priv, tran, _PSR_IIR_A)
+#define TRANS_PSR_IIR(dev_priv, tran)                  _MMIO_TRANS2(dev_priv, tran, _PSR_IIR_A)
 #define   _EDP_PSR_TRANS_SHIFT(trans)          ((trans) == TRANSCODER_EDP ? \
                                                 0 : ((trans) - TRANSCODER_A + 1) * 8)
 #define   TGL_PSR_MASK                 REG_GENMASK(2, 0)