return;
}
- gen9_set_dc_state(display, DC_STATE_DISABLE);
-
- if (!HAS_DISPLAY(display))
+ if (HAS_DISPLAY(display)) {
+ intel_dmc_wl_get_noreg(display);
+ gen9_set_dc_state(display, DC_STATE_DISABLE);
+ intel_dmc_wl_put_noreg(display);
+ } else {
+ gen9_set_dc_state(display, DC_STATE_DISABLE);
return;
+ }
intel_dmc_wl_disable(display);
if (!__intel_dmc_wl_supported(display))
return;
- if (!intel_dmc_wl_check_range(reg))
+ if (i915_mmio_reg_valid(reg) && !intel_dmc_wl_check_range(reg))
return;
spin_lock_irqsave(&wl->lock, flags);
if (!__intel_dmc_wl_supported(display))
return;
- if (!intel_dmc_wl_check_range(reg))
+ if (i915_mmio_reg_valid(reg) && !intel_dmc_wl_check_range(reg))
return;
spin_lock_irqsave(&wl->lock, flags);
out_unlock:
spin_unlock_irqrestore(&wl->lock, flags);
}
+
+void intel_dmc_wl_get_noreg(struct intel_display *display)
+{
+ intel_dmc_wl_get(display, INVALID_MMIO_REG);
+}
+
+void intel_dmc_wl_put_noreg(struct intel_display *display)
+{
+ intel_dmc_wl_put(display, INVALID_MMIO_REG);
+}
void intel_dmc_wl_disable(struct intel_display *display);
void intel_dmc_wl_get(struct intel_display *display, i915_reg_t reg);
void intel_dmc_wl_put(struct intel_display *display, i915_reg_t reg);
+void intel_dmc_wl_get_noreg(struct intel_display *display);
+void intel_dmc_wl_put_noreg(struct intel_display *display);
#endif /* __INTEL_WAKELOCK_H__ */