ARM: dts: lan966x: add basic Kontron KSwitch D10 support

Add basic support for the Kontron KSwitch D10 MMT. It comes in two
variants: "6G-2GS" which features 6 Gigabit copper ports and two SFP
cages and "8G" which features 6 Gigbabit copper ports (where two are
2.5G capable).

For now the following is supported and working:
 - Kernel console
 - SFP cages
 - SPI
 - SGPIO
 - Watchdog

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
[claudiu.beznea: fixed conflict on Makefile]
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220502224127.2604333-8-michael@walle.cc
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 7c16f8a..54beef7 100644 (file)
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -742,7 +742,9 @@ dtb-$(CONFIG_SOC_IMX7ULP) += \
        imx7ulp-com.dtb \
        imx7ulp-evk.dtb
 dtb-$(CONFIG_SOC_LAN966) += \
-       lan966x-pcb8291.dtb
+       lan966x-pcb8291.dtb \
+       lan966x-kontron-kswitch-d10-mmt-6g-2gs.dtb \
+       lan966x-kontron-kswitch-d10-mmt-8g.dtb
 dtb-$(CONFIG_SOC_LS1021A) += \
        ls1021a-moxa-uc-8410a.dtb \
        ls1021a-qds.dtb \

diff --git a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts
new file mode 100644 (file)
index 0000000..7b12cbe
--- /dev/null
+++ b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree file for the Kontron KSwitch D10 MMT 6G-2GS
+ */
+
+/dts-v1/;
+#include "lan966x-kontron-kswitch-d10-mmt.dtsi"
+
+/ {
+       model = "Kontron KSwitch D10 MMT 6G-2GS";
+       compatible = "kontron,kswitch-d10-mmt-6g-2gs", "kontron,s1921",
+                    "microchip,lan9668", "microchip,lan966";
+
+       aliases {
+               i2c0 = &i2c4;
+               i2c1 = &i2c1;
+       };
+
+       sfp0: sfp0 {
+               compatible = "sff,sfp";
+               i2c-bus = <&i2c4>;
+               los-gpios = <&sgpio_in 1 0 GPIO_ACTIVE_HIGH>;
+               mod-def0-gpios = <&sgpio_in 1 1 GPIO_ACTIVE_LOW>;
+               maximum-power-milliwatt = <2500>;
+               tx-disable-gpios = <&sgpio_out 3 0 GPIO_ACTIVE_LOW>;
+               tx-fault-gpios = <&sgpio_in 0 2 GPIO_ACTIVE_HIGH>;
+               rate-select0-gpios = <&sgpio_out 2 0 GPIO_ACTIVE_HIGH>;
+               rate-select1-gpios = <&sgpio_out 2 1 GPIO_ACTIVE_HIGH>;
+       };
+
+       sfp1: sfp1 {
+               compatible = "sff,sfp";
+               i2c-bus = <&i2c1>;
+               los-gpios = <&sgpio_in 1 2 GPIO_ACTIVE_HIGH>;
+               mod-def0-gpios = <&sgpio_in 1 3 GPIO_ACTIVE_LOW>;
+               maximum-power-milliwatt = <2500>;
+               tx-disable-gpios = <&sgpio_out 3 1 GPIO_ACTIVE_LOW>;
+               tx-fault-gpios = <&sgpio_in 0 3 GPIO_ACTIVE_HIGH>;
+               rate-select0-gpios = <&sgpio_out 2 2 GPIO_ACTIVE_HIGH>;
+               rate-select1-gpios = <&sgpio_out 2 3 GPIO_ACTIVE_HIGH>;
+       };
+};
+
+&flx1 {
+       atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
+       status = "okay";
+
+       i2c1: i2c@600 {
+               pinctrl-0 = <&fc1_c_pins>;
+               pinctrl-names = "default";
+               status = "okay";
+       };
+};
+
+&flx4 {
+       atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
+       status = "okay";
+
+       i2c4: i2c@600 {
+               pinctrl-0 = <&fc4_b_pins>;
+               pinctrl-names = "default";
+               status = "okay";
+       };
+};
+
+&gpio {
+       fc1_c_pins: fc1-c-i2c-pins {
+               /* SCL, SDA */
+               pins = "GPIO_47", "GPIO_48";
+               function = "fc1_c";
+       };
+
+       fc4_b_pins: fc4-b-i2c-pins {
+               /* SCL, SDA */
+               pins = "GPIO_57", "GPIO_58";
+               function = "fc4_b";
+       };
+};

diff --git a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts
new file mode 100644 (file)
index 0000000..4b35f6c
--- /dev/null
+++ b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree file for the Kontron KSwitch D10 MMT 8G
+ */
+
+/dts-v1/;
+#include "lan966x-kontron-kswitch-d10-mmt.dtsi"
+
+/ {
+       model = "Kontron KSwitch D10 MMT 8G";
+       compatible = "kontron,kswitch-d10-mmt-8g", "kontron,s1921",
+                    "microchip,lan9668", "microchip,lan966";
+};

diff --git a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi
new file mode 100644 (file)
index 0000000..4c1ebb4
--- /dev/null
+++ b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi
@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Common part of the device tree for the Kontron KSwitch D10 MMT
+ */
+
+/dts-v1/;
+#include "lan966x.dtsi"
+
+/ {
+       aliases {
+               serial0 = &usart0;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
+       gpio-restart {
+               compatible = "gpio-restart";
+               gpios = <&gpio 56 GPIO_ACTIVE_LOW>;
+               priority = <200>;
+       };
+};
+
+&flx0 {
+       atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
+       status = "okay";
+
+       usart0: serial@200 {
+               pinctrl-0 = <&usart0_pins>;
+               pinctrl-names = "default";
+               status = "okay";
+       };
+};
+
+&flx3 {
+       atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>;
+       status = "okay";
+
+       spi3: spi@400 {
+               pinctrl-0 = <&fc3_b_pins>;
+               pinctrl-names = "default";
+               status = "okay";
+               cs-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
+       };
+};
+
+&gpio {
+       fc3_b_pins: fc3-b-pins {
+               /* SCK, MISO, MOSI */
+               pins = "GPIO_51", "GPIO_52", "GPIO_53";
+               function = "fc3_b";
+       };
+
+       sgpio_a_pins: sgpio-a-pins {
+               /* SCK, D0, D1 */
+               pins = "GPIO_32", "GPIO_33", "GPIO_34";
+               function = "sgpio_a";
+       };
+
+       sgpio_b_pins: sgpio-b-pins {
+               /* LD */
+               pins = "GPIO_64";
+               function = "sgpio_b";
+       };
+
+       usart0_pins: usart0-pins {
+               /* RXD, TXD */
+               pins = "GPIO_25", "GPIO_26";
+               function = "fc0_b";
+       };
+};
+
+&sgpio {
+       pinctrl-0 = <&sgpio_a_pins>, <&sgpio_b_pins>;
+       pinctrl-names = "default";
+       bus-frequency = <8000000>;
+       /* arbitrary range because all GPIOs are in software mode */
+       microchip,sgpio-port-ranges = <0 11>;
+       status = "okay";
+
+       sgpio_in: gpio@0 {
+               ngpios = <128>;
+       };
+
+       sgpio_out: gpio@1 {
+               ngpios = <128>;
+       };
+};
+
+&watchdog {
+       status = "okay";
+};