ARM: S5PC100: Move gpio support from plat-s5pc1xx to mach-s5pc100
authorMarek Szyprowski <m.szyprowski@samsung.com>
Tue, 18 May 2010 10:38:41 +0000 (12:38 +0200)
committerBen Dooks <ben-linux@fluff.org>
Wed, 19 May 2010 09:23:11 +0000 (18:23 +0900)
Move gpio-lib support from plat-s5pc1xx to mach-s5pc100. Only basic gpio
functionality is now supported. Gpio interrupts are disabled temporarly
and will be added later.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
arch/arm/mach-s5pc100/Makefile
arch/arm/mach-s5pc100/gpiolib.c [new file with mode: 0644]
arch/arm/mach-s5pc100/include/mach/regs-gpio.h [new file with mode: 0644]
arch/arm/mach-s5pc100/mach-smdkc100.c
arch/arm/plat-s5pc1xx/Makefile
arch/arm/plat-s5pc1xx/gpiolib.c [deleted file]
arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h [deleted file]

index 809ff10..4199ce2 100644 (file)
@@ -11,7 +11,7 @@ obj-                          :=
 
 # Core support for S5PC100 system
 
-obj-$(CONFIG_CPU_S5PC100)      += cpu.o
+obj-$(CONFIG_CPU_S5PC100)      += cpu.o gpiolib.o
 
 # Helper and device support
 
diff --git a/arch/arm/mach-s5pc100/gpiolib.c b/arch/arm/mach-s5pc100/gpiolib.c
new file mode 100644 (file)
index 0000000..c8e8336
--- /dev/null
@@ -0,0 +1,428 @@
+/*
+ * arch/arm/plat-s5pc1xx/gpiolib.c
+ *
+ *  Copyright 2009 Samsung Electronics Co
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * S5PC1XX - GPIOlib support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+
+#include <mach/map.h>
+#include <mach/regs-gpio.h>
+
+#include <plat/gpio-core.h>
+#include <plat/gpio-cfg.h>
+#include <plat/gpio-cfg-helpers.h>
+
+/* S5PC100 GPIO bank summary:
+ *
+ * Bank        GPIOs   Style   INT Type
+ * A0  8       4Bit    GPIO_INT0
+ * A1  5       4Bit    GPIO_INT1
+ * B   8       4Bit    GPIO_INT2
+ * C   5       4Bit    GPIO_INT3
+ * D   7       4Bit    GPIO_INT4
+ * E0  8       4Bit    GPIO_INT5
+ * E1  6       4Bit    GPIO_INT6
+ * F0  8       4Bit    GPIO_INT7
+ * F1  8       4Bit    GPIO_INT8
+ * F2  8       4Bit    GPIO_INT9
+ * F3  4       4Bit    GPIO_INT10
+ * G0  8       4Bit    GPIO_INT11
+ * G1  3       4Bit    GPIO_INT12
+ * G2  7       4Bit    GPIO_INT13
+ * G3  7       4Bit    GPIO_INT14
+ * H0  8       4Bit    WKUP_INT
+ * H1  8       4Bit    WKUP_INT
+ * H2  8       4Bit    WKUP_INT
+ * H3  8       4Bit    WKUP_INT
+ * I   8       4Bit    GPIO_INT15
+ * J0  8       4Bit    GPIO_INT16
+ * J1  5       4Bit    GPIO_INT17
+ * J2  8       4Bit    GPIO_INT18
+ * J3  8       4Bit    GPIO_INT19
+ * J4  4       4Bit    GPIO_INT20
+ * K0  8       4Bit    None
+ * K1  6       4Bit    None
+ * K2  8       4Bit    None
+ * K3  8       4Bit    None
+ * L0  8       4Bit    None
+ * L1  8       4Bit    None
+ * L2  8       4Bit    None
+ * L3  8       4Bit    None
+ */
+
+#if 0
+static int s5pc1xx_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
+{
+       return S3C_IRQ_GPIO(chip->base + offset);
+}
+
+static int s5pc1xx_gpiolib_to_eint(struct gpio_chip *chip, unsigned int offset)
+{
+       int base;
+
+       base = chip->base - S5PC100_GPH0(0);
+       if (base == 0)
+               return IRQ_EINT(offset);
+       base = chip->base - S5PC100_GPH1(0);
+       if (base == 0)
+               return IRQ_EINT(8 + offset);
+       base = chip->base - S5PC100_GPH2(0);
+       if (base == 0)
+               return IRQ_EINT(16 + offset);
+       base = chip->base - S5PC100_GPH3(0);
+       if (base == 0)
+               return IRQ_EINT(24 + offset);
+       return -EINVAL;
+}
+#endif
+static struct s3c_gpio_cfg gpio_cfg = {
+       .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
+       .set_pull       = s3c_gpio_setpull_updown,
+       .get_pull       = s3c_gpio_getpull_updown,
+};
+
+static struct s3c_gpio_cfg gpio_cfg_eint = {
+       .cfg_eint       = 0xf,
+       .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
+       .set_pull       = s3c_gpio_setpull_updown,
+       .get_pull       = s3c_gpio_getpull_updown,
+};
+
+static struct s3c_gpio_cfg gpio_cfg_noint = {
+       .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
+       .set_pull       = s3c_gpio_setpull_updown,
+       .get_pull       = s3c_gpio_getpull_updown,
+};
+
+static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
+       {
+               .base   = S5PC100_GPA0_BASE,
+               .config = &gpio_cfg,
+               .chip   = {
+                       .base   = S5PC100_GPA0(0),
+                       .ngpio  = S5PC100_GPIO_A0_NR,
+                       .label  = "GPA0",
+               },
+       }, {
+               .base   = S5PC100_GPA1_BASE,
+               .config = &gpio_cfg,
+               .chip   = {
+                       .base   = S5PC100_GPA1(0),
+                       .ngpio  = S5PC100_GPIO_A1_NR,
+                       .label  = "GPA1",
+               },
+       }, {
+               .base   = S5PC100_GPB_BASE,
+               .config = &gpio_cfg,
+               .chip   = {
+                       .base   = S5PC100_GPB(0),
+                       .ngpio  = S5PC100_GPIO_B_NR,
+                       .label  = "GPB",
+               },
+       }, {
+               .base   = S5PC100_GPC_BASE,
+               .config = &gpio_cfg,
+               .chip   = {
+                       .base   = S5PC100_GPC(0),
+                       .ngpio  = S5PC100_GPIO_C_NR,
+                       .label  = "GPC",
+               },
+       }, {
+               .base   = S5PC100_GPD_BASE,
+               .config = &gpio_cfg,
+               .chip   = {
+                       .base   = S5PC100_GPD(0),
+                       .ngpio  = S5PC100_GPIO_D_NR,
+                       .label  = "GPD",
+               },
+       }, {
+               .base   = S5PC100_GPE0_BASE,
+               .config = &gpio_cfg,
+               .chip   = {
+                       .base   = S5PC100_GPE0(0),
+                       .ngpio  = S5PC100_GPIO_E0_NR,
+                       .label  = "GPE0",
+               },
+       }, {
+               .base   = S5PC100_GPE1_BASE,
+               .config = &gpio_cfg,
+               .chip   = {
+                       .base   = S5PC100_GPE1(0),
+                       .ngpio  = S5PC100_GPIO_E1_NR,
+                       .label  = "GPE1",
+               },
+       }, {
+               .base   = S5PC100_GPF0_BASE,
+               .config = &gpio_cfg,
+               .chip   = {
+                       .base   = S5PC100_GPF0(0),
+                       .ngpio  = S5PC100_GPIO_F0_NR,
+                       .label  = "GPF0",
+               },
+       }, {
+               .base   = S5PC100_GPF1_BASE,
+               .config = &gpio_cfg,
+               .chip   = {
+                       .base   = S5PC100_GPF1(0),
+                       .ngpio  = S5PC100_GPIO_F1_NR,
+                       .label  = "GPF1",
+               },
+       }, {
+               .base   = S5PC100_GPF2_BASE,
+               .config = &gpio_cfg,
+               .chip   = {
+                       .base   = S5PC100_GPF2(0),
+                       .ngpio  = S5PC100_GPIO_F2_NR,
+                       .label  = "GPF2",
+               },
+       }, {
+               .base   = S5PC100_GPF3_BASE,
+               .config = &gpio_cfg,
+               .chip   = {
+                       .base   = S5PC100_GPF3(0),
+                       .ngpio  = S5PC100_GPIO_F3_NR,
+                       .label  = "GPF3",
+               },
+       }, {
+               .base   = S5PC100_GPG0_BASE,
+               .config = &gpio_cfg,
+               .chip   = {
+                       .base   = S5PC100_GPG0(0),
+                       .ngpio  = S5PC100_GPIO_G0_NR,
+                       .label  = "GPG0",
+               },
+       }, {
+               .base   = S5PC100_GPG1_BASE,
+               .config = &gpio_cfg,
+               .chip   = {
+                       .base   = S5PC100_GPG1(0),
+                       .ngpio  = S5PC100_GPIO_G1_NR,
+                       .label  = "GPG1",
+               },
+       }, {
+               .base   = S5PC100_GPG2_BASE,
+               .config = &gpio_cfg,
+               .chip   = {
+                       .base   = S5PC100_GPG2(0),
+                       .ngpio  = S5PC100_GPIO_G2_NR,
+                       .label  = "GPG2",
+               },
+       }, {
+               .base   = S5PC100_GPG3_BASE,
+               .config = &gpio_cfg,
+               .chip   = {
+                       .base   = S5PC100_GPG3(0),
+                       .ngpio  = S5PC100_GPIO_G3_NR,
+                       .label  = "GPG3",
+               },
+       }, {
+               .base   = S5PC100_GPH0_BASE,
+               .config = &gpio_cfg_eint,
+               .chip   = {
+                       .base   = S5PC100_GPH0(0),
+                       .ngpio  = S5PC100_GPIO_H0_NR,
+                       .label  = "GPH0",
+               },
+       }, {
+               .base   = S5PC100_GPH1_BASE,
+               .config = &gpio_cfg_eint,
+               .chip   = {
+                       .base   = S5PC100_GPH1(0),
+                       .ngpio  = S5PC100_GPIO_H1_NR,
+                       .label  = "GPH1",
+               },
+       }, {
+               .base   = S5PC100_GPH2_BASE,
+               .config = &gpio_cfg_eint,
+               .chip   = {
+                       .base   = S5PC100_GPH2(0),
+                       .ngpio  = S5PC100_GPIO_H2_NR,
+                       .label  = "GPH2",
+               },
+       }, {
+               .base   = S5PC100_GPH3_BASE,
+               .config = &gpio_cfg_eint,
+               .chip   = {
+                       .base   = S5PC100_GPH3(0),
+                       .ngpio  = S5PC100_GPIO_H3_NR,
+                       .label  = "GPH3",
+               },
+       }, {
+               .base   = S5PC100_GPI_BASE,
+               .config = &gpio_cfg,
+               .chip   = {
+                       .base   = S5PC100_GPI(0),
+                       .ngpio  = S5PC100_GPIO_I_NR,
+                       .label  = "GPI",
+               },
+       }, {
+               .base   = S5PC100_GPJ0_BASE,
+               .config = &gpio_cfg,
+               .chip   = {
+                       .base   = S5PC100_GPJ0(0),
+                       .ngpio  = S5PC100_GPIO_J0_NR,
+                       .label  = "GPJ0",
+               },
+       }, {
+               .base   = S5PC100_GPJ1_BASE,
+               .config = &gpio_cfg,
+               .chip   = {
+                       .base   = S5PC100_GPJ1(0),
+                       .ngpio  = S5PC100_GPIO_J1_NR,
+                       .label  = "GPJ1",
+               },
+       }, {
+               .base   = S5PC100_GPJ2_BASE,
+               .config = &gpio_cfg,
+               .chip   = {
+                       .base   = S5PC100_GPJ2(0),
+                       .ngpio  = S5PC100_GPIO_J2_NR,
+                       .label  = "GPJ2",
+               },
+       }, {
+               .base   = S5PC100_GPJ3_BASE,
+               .config = &gpio_cfg,
+               .chip   = {
+                       .base   = S5PC100_GPJ3(0),
+                       .ngpio  = S5PC100_GPIO_J3_NR,
+                       .label  = "GPJ3",
+               },
+       }, {
+               .base   = S5PC100_GPJ4_BASE,
+               .config = &gpio_cfg,
+               .chip   = {
+                       .base   = S5PC100_GPJ4(0),
+                       .ngpio  = S5PC100_GPIO_J4_NR,
+                       .label  = "GPJ4",
+               },
+       }, {
+               .base   = S5PC100_GPK0_BASE,
+               .config = &gpio_cfg_noint,
+               .chip   = {
+                       .base   = S5PC100_GPK0(0),
+                       .ngpio  = S5PC100_GPIO_K0_NR,
+                       .label  = "GPK0",
+               },
+       }, {
+               .base   = S5PC100_GPK1_BASE,
+               .config = &gpio_cfg_noint,
+               .chip   = {
+                       .base   = S5PC100_GPK1(0),
+                       .ngpio  = S5PC100_GPIO_K1_NR,
+                       .label  = "GPK1",
+               },
+       }, {
+               .base   = S5PC100_GPK2_BASE,
+               .config = &gpio_cfg_noint,
+               .chip   = {
+                       .base   = S5PC100_GPK2(0),
+                       .ngpio  = S5PC100_GPIO_K2_NR,
+                       .label  = "GPK2",
+               },
+       }, {
+               .base   = S5PC100_GPK3_BASE,
+               .config = &gpio_cfg_noint,
+               .chip   = {
+                       .base   = S5PC100_GPK3(0),
+                       .ngpio  = S5PC100_GPIO_K3_NR,
+                       .label  = "GPK3",
+               },
+       }, {
+               .base   = S5PC100_GPL0_BASE,
+               .config = &gpio_cfg_noint,
+               .chip   = {
+                       .base   = S5PC100_GPL0(0),
+                       .ngpio  = S5PC100_GPIO_L0_NR,
+                       .label  = "GPL0",
+               },
+       }, {
+               .base   = S5PC100_GPL1_BASE,
+               .config = &gpio_cfg_noint,
+               .chip   = {
+                       .base   = S5PC100_GPL1(0),
+                       .ngpio  = S5PC100_GPIO_L1_NR,
+                       .label  = "GPL1",
+               },
+       }, {
+               .base   = S5PC100_GPL2_BASE,
+               .config = &gpio_cfg_noint,
+               .chip   = {
+                       .base   = S5PC100_GPL2(0),
+                       .ngpio  = S5PC100_GPIO_L2_NR,
+                       .label  = "GPL2",
+               },
+       }, {
+               .base   = S5PC100_GPL3_BASE,
+               .config = &gpio_cfg_noint,
+               .chip   = {
+                       .base   = S5PC100_GPL3(0),
+                       .ngpio  = S5PC100_GPIO_L3_NR,
+                       .label  = "GPL3",
+               },
+       }, {
+               .base   = S5PC100_GPL4_BASE,
+               .config = &gpio_cfg_noint,
+               .chip   = {
+                       .base   = S5PC100_GPL4(0),
+                       .ngpio  = S5PC100_GPIO_L4_NR,
+                       .label  = "GPL4",
+               },
+       },
+};
+
+/* FIXME move from irq-gpio.c */
+extern struct irq_chip s5pc1xx_gpioint;
+extern void s5pc1xx_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc);
+
+static __init void s5pc100_gpiolib_link(struct s3c_gpio_chip *chip)
+{
+#if 0
+       /* Interrupt */
+       if (chip->config == &gpio_cfg) {
+               int i, irq;
+
+               chip->chip.to_irq = s5pc1xx_gpiolib_to_irq;
+
+               for (i = 0;  i < chip->chip.ngpio; i++) {
+                       irq = S3C_IRQ_GPIO_BASE + chip->chip.base + i;
+                       set_irq_chip(irq, &s5pc1xx_gpioint);
+                       set_irq_data(irq, &chip->chip);
+                       set_irq_handler(irq, handle_level_irq);
+                       set_irq_flags(irq, IRQF_VALID);
+               }
+       } else if (chip->config == &gpio_cfg_eint)
+               chip->chip.to_irq = s5pc1xx_gpiolib_to_eint;
+#endif
+}
+
+static __init int s5pc1xx_gpiolib_init(void)
+{
+       struct s3c_gpio_chip *chip;
+       int nr_chips;
+
+       chip = s5pc100_gpio_chips;
+       nr_chips = ARRAY_SIZE(s5pc100_gpio_chips);
+
+       for (; nr_chips > 0; nr_chips--, chip++)
+               s5pc100_gpiolib_link(chip);
+
+       samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips,
+                                      ARRAY_SIZE(s5pc100_gpio_chips));
+#if 0
+       /* Interrupt */
+       set_irq_chained_handler(IRQ_GPIOINT, s5pc1xx_irq_gpioint_handler);
+#endif
+       return 0;
+}
+core_initcall(s5pc1xx_gpiolib_init);
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-gpio.h b/arch/arm/mach-s5pc100/include/mach/regs-gpio.h
new file mode 100644 (file)
index 0000000..43c7bc8
--- /dev/null
@@ -0,0 +1,70 @@
+/* linux/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * S5PC1XX - GPIO register definitions
+ */
+
+#ifndef __ASM_PLAT_S5PC1XX_REGS_GPIO_H
+#define __ASM_PLAT_S5PC1XX_REGS_GPIO_H __FILE__
+
+#include <mach/map.h>
+
+/* S5PC100 */
+#define S5PC100_GPIO_BASE      S5PC1XX_VA_GPIO
+#define S5PC100_GPA0_BASE      (S5PC100_GPIO_BASE + 0x0000)
+#define S5PC100_GPA1_BASE      (S5PC100_GPIO_BASE + 0x0020)
+#define S5PC100_GPB_BASE       (S5PC100_GPIO_BASE + 0x0040)
+#define S5PC100_GPC_BASE       (S5PC100_GPIO_BASE + 0x0060)
+#define S5PC100_GPD_BASE       (S5PC100_GPIO_BASE + 0x0080)
+#define S5PC100_GPE0_BASE      (S5PC100_GPIO_BASE + 0x00A0)
+#define S5PC100_GPE1_BASE      (S5PC100_GPIO_BASE + 0x00C0)
+#define S5PC100_GPF0_BASE      (S5PC100_GPIO_BASE + 0x00E0)
+#define S5PC100_GPF1_BASE      (S5PC100_GPIO_BASE + 0x0100)
+#define S5PC100_GPF2_BASE      (S5PC100_GPIO_BASE + 0x0120)
+#define S5PC100_GPF3_BASE      (S5PC100_GPIO_BASE + 0x0140)
+#define S5PC100_GPG0_BASE      (S5PC100_GPIO_BASE + 0x0160)
+#define S5PC100_GPG1_BASE      (S5PC100_GPIO_BASE + 0x0180)
+#define S5PC100_GPG2_BASE      (S5PC100_GPIO_BASE + 0x01A0)
+#define S5PC100_GPG3_BASE      (S5PC100_GPIO_BASE + 0x01C0)
+#define S5PC100_GPH0_BASE      (S5PC100_GPIO_BASE + 0x0C00)
+#define S5PC100_GPH1_BASE      (S5PC100_GPIO_BASE + 0x0C20)
+#define S5PC100_GPH2_BASE      (S5PC100_GPIO_BASE + 0x0C40)
+#define S5PC100_GPH3_BASE      (S5PC100_GPIO_BASE + 0x0C60)
+#define S5PC100_GPI_BASE       (S5PC100_GPIO_BASE + 0x01E0)
+#define S5PC100_GPJ0_BASE      (S5PC100_GPIO_BASE + 0x0200)
+#define S5PC100_GPJ1_BASE      (S5PC100_GPIO_BASE + 0x0220)
+#define S5PC100_GPJ2_BASE      (S5PC100_GPIO_BASE + 0x0240)
+#define S5PC100_GPJ3_BASE      (S5PC100_GPIO_BASE + 0x0260)
+#define S5PC100_GPJ4_BASE      (S5PC100_GPIO_BASE + 0x0280)
+#define S5PC100_GPK0_BASE      (S5PC100_GPIO_BASE + 0x02A0)
+#define S5PC100_GPK1_BASE      (S5PC100_GPIO_BASE + 0x02C0)
+#define S5PC100_GPK2_BASE      (S5PC100_GPIO_BASE + 0x02E0)
+#define S5PC100_GPK3_BASE      (S5PC100_GPIO_BASE + 0x0300)
+#define S5PC100_GPL0_BASE      (S5PC100_GPIO_BASE + 0x0320)
+#define S5PC100_GPL1_BASE      (S5PC100_GPIO_BASE + 0x0340)
+#define S5PC100_GPL2_BASE      (S5PC100_GPIO_BASE + 0x0360)
+#define S5PC100_GPL3_BASE      (S5PC100_GPIO_BASE + 0x0380)
+#define S5PC100_GPL4_BASE      (S5PC100_GPIO_BASE + 0x03A0)
+#define S5PC100_EINT_BASE      (S5PC100_GPIO_BASE + 0x0E00)
+
+#define S5PC100_UHOST          (S5PC100_GPIO_BASE + 0x0B68)
+#define S5PC100_PDNEN          (S5PC100_GPIO_BASE + 0x0F80)
+
+/* PDNEN */
+#define S5PC100_PDNEN_CFG_PDNEN        (1 << 1)
+#define S5PC100_PDNEN_CFG_AUTO (0 << 1)
+#define S5PC100_PDNEN_POWERDOWN        (1 << 0)
+#define S5PC100_PDNEN_NORMAL   (0 << 0)
+
+/* Common part */
+/* External interrupt base is same at both s5pc100 and s5pc110 */
+#define S5PC1XX_EINT_BASE      (S5PC100_EINT_BASE)
+
+#define S5PC100_GPx_INPUT(__gpio)      (0x0 << ((__gpio) * 4))
+#define S5PC100_GPx_OUTPUT(__gpio)     (0x1 << ((__gpio) * 4))
+#define S5PC100_GPx_CONMASK(__gpio)    (0xf << ((__gpio) * 4))
+
+#endif /* __ASM_PLAT_S5PC1XX_REGS_GPIO_H */
+
index ae3c52c..bfe67db 100644 (file)
@@ -35,7 +35,6 @@
 
 #include <plat/regs-serial.h>
 #include <plat/gpio-cfg.h>
-#include <plat/regs-gpio.h>
 
 #include <plat/clock.h>
 #include <plat/devs.h>
index 66a8f3e..540fca5 100644 (file)
@@ -13,9 +13,8 @@ obj-                          :=
 
 obj-y                          += dev-uart.o
 obj-y                          += cpu.o
-obj-y                          += irq.o irq-gpio.o irq-eint.o
+obj-y                          += irq.o
 obj-y                          += clock.o
-obj-y                          += gpiolib.o
 
 # CPU support
 
diff --git a/arch/arm/plat-s5pc1xx/gpiolib.c b/arch/arm/plat-s5pc1xx/gpiolib.c
deleted file mode 100644 (file)
index 5a97a8f..0000000
+++ /dev/null
@@ -1,425 +0,0 @@
-/*
- * arch/arm/plat-s5pc1xx/gpiolib.c
- *
- *  Copyright 2009 Samsung Electronics Co
- *  Kyungmin Park <kyungmin.park@samsung.com>
- *
- * S5PC1XX - GPIOlib support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-
-#include <mach/map.h>
-
-#include <plat/gpio-core.h>
-#include <plat/gpio-cfg.h>
-#include <plat/gpio-cfg-helpers.h>
-#include <plat/regs-gpio.h>
-
-/* S5PC100 GPIO bank summary:
- *
- * Bank        GPIOs   Style   INT Type
- * A0  8       4Bit    GPIO_INT0
- * A1  5       4Bit    GPIO_INT1
- * B   8       4Bit    GPIO_INT2
- * C   5       4Bit    GPIO_INT3
- * D   7       4Bit    GPIO_INT4
- * E0  8       4Bit    GPIO_INT5
- * E1  6       4Bit    GPIO_INT6
- * F0  8       4Bit    GPIO_INT7
- * F1  8       4Bit    GPIO_INT8
- * F2  8       4Bit    GPIO_INT9
- * F3  4       4Bit    GPIO_INT10
- * G0  8       4Bit    GPIO_INT11
- * G1  3       4Bit    GPIO_INT12
- * G2  7       4Bit    GPIO_INT13
- * G3  7       4Bit    GPIO_INT14
- * H0  8       4Bit    WKUP_INT
- * H1  8       4Bit    WKUP_INT
- * H2  8       4Bit    WKUP_INT
- * H3  8       4Bit    WKUP_INT
- * I   8       4Bit    GPIO_INT15
- * J0  8       4Bit    GPIO_INT16
- * J1  5       4Bit    GPIO_INT17
- * J2  8       4Bit    GPIO_INT18
- * J3  8       4Bit    GPIO_INT19
- * J4  4       4Bit    GPIO_INT20
- * K0  8       4Bit    None
- * K1  6       4Bit    None
- * K2  8       4Bit    None
- * K3  8       4Bit    None
- * L0  8       4Bit    None
- * L1  8       4Bit    None
- * L2  8       4Bit    None
- * L3  8       4Bit    None
- */
-
-static int s5pc1xx_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
-{
-       return S3C_IRQ_GPIO(chip->base + offset);
-}
-
-static int s5pc1xx_gpiolib_to_eint(struct gpio_chip *chip, unsigned int offset)
-{
-       int base;
-
-       base = chip->base - S5PC100_GPH0(0);
-       if (base == 0)
-               return IRQ_EINT(offset);
-       base = chip->base - S5PC100_GPH1(0);
-       if (base == 0)
-               return IRQ_EINT(8 + offset);
-       base = chip->base - S5PC100_GPH2(0);
-       if (base == 0)
-               return IRQ_EINT(16 + offset);
-       base = chip->base - S5PC100_GPH3(0);
-       if (base == 0)
-               return IRQ_EINT(24 + offset);
-       return -EINVAL;
-}
-
-static struct s3c_gpio_cfg gpio_cfg = {
-       .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
-       .set_pull       = s3c_gpio_setpull_updown,
-       .get_pull       = s3c_gpio_getpull_updown,
-};
-
-static struct s3c_gpio_cfg gpio_cfg_eint = {
-       .cfg_eint       = 0xf,
-       .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
-       .set_pull       = s3c_gpio_setpull_updown,
-       .get_pull       = s3c_gpio_getpull_updown,
-};
-
-static struct s3c_gpio_cfg gpio_cfg_noint = {
-       .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
-       .set_pull       = s3c_gpio_setpull_updown,
-       .get_pull       = s3c_gpio_getpull_updown,
-};
-
-static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
-       {
-               .base   = S5PC100_GPA0_BASE,
-               .config = &gpio_cfg,
-               .chip   = {
-                       .base   = S5PC100_GPA0(0),
-                       .ngpio  = S5PC100_GPIO_A0_NR,
-                       .label  = "GPA0",
-               },
-       }, {
-               .base   = S5PC100_GPA1_BASE,
-               .config = &gpio_cfg,
-               .chip   = {
-                       .base   = S5PC100_GPA1(0),
-                       .ngpio  = S5PC100_GPIO_A1_NR,
-                       .label  = "GPA1",
-               },
-       }, {
-               .base   = S5PC100_GPB_BASE,
-               .config = &gpio_cfg,
-               .chip   = {
-                       .base   = S5PC100_GPB(0),
-                       .ngpio  = S5PC100_GPIO_B_NR,
-                       .label  = "GPB",
-               },
-       }, {
-               .base   = S5PC100_GPC_BASE,
-               .config = &gpio_cfg,
-               .chip   = {
-                       .base   = S5PC100_GPC(0),
-                       .ngpio  = S5PC100_GPIO_C_NR,
-                       .label  = "GPC",
-               },
-       }, {
-               .base   = S5PC100_GPD_BASE,
-               .config = &gpio_cfg,
-               .chip   = {
-                       .base   = S5PC100_GPD(0),
-                       .ngpio  = S5PC100_GPIO_D_NR,
-                       .label  = "GPD",
-               },
-       }, {
-               .base   = S5PC100_GPE0_BASE,
-               .config = &gpio_cfg,
-               .chip   = {
-                       .base   = S5PC100_GPE0(0),
-                       .ngpio  = S5PC100_GPIO_E0_NR,
-                       .label  = "GPE0",
-               },
-       }, {
-               .base   = S5PC100_GPE1_BASE,
-               .config = &gpio_cfg,
-               .chip   = {
-                       .base   = S5PC100_GPE1(0),
-                       .ngpio  = S5PC100_GPIO_E1_NR,
-                       .label  = "GPE1",
-               },
-       }, {
-               .base   = S5PC100_GPF0_BASE,
-               .config = &gpio_cfg,
-               .chip   = {
-                       .base   = S5PC100_GPF0(0),
-                       .ngpio  = S5PC100_GPIO_F0_NR,
-                       .label  = "GPF0",
-               },
-       }, {
-               .base   = S5PC100_GPF1_BASE,
-               .config = &gpio_cfg,
-               .chip   = {
-                       .base   = S5PC100_GPF1(0),
-                       .ngpio  = S5PC100_GPIO_F1_NR,
-                       .label  = "GPF1",
-               },
-       }, {
-               .base   = S5PC100_GPF2_BASE,
-               .config = &gpio_cfg,
-               .chip   = {
-                       .base   = S5PC100_GPF2(0),
-                       .ngpio  = S5PC100_GPIO_F2_NR,
-                       .label  = "GPF2",
-               },
-       }, {
-               .base   = S5PC100_GPF3_BASE,
-               .config = &gpio_cfg,
-               .chip   = {
-                       .base   = S5PC100_GPF3(0),
-                       .ngpio  = S5PC100_GPIO_F3_NR,
-                       .label  = "GPF3",
-               },
-       }, {
-               .base   = S5PC100_GPG0_BASE,
-               .config = &gpio_cfg,
-               .chip   = {
-                       .base   = S5PC100_GPG0(0),
-                       .ngpio  = S5PC100_GPIO_G0_NR,
-                       .label  = "GPG0",
-               },
-       }, {
-               .base   = S5PC100_GPG1_BASE,
-               .config = &gpio_cfg,
-               .chip   = {
-                       .base   = S5PC100_GPG1(0),
-                       .ngpio  = S5PC100_GPIO_G1_NR,
-                       .label  = "GPG1",
-               },
-       }, {
-               .base   = S5PC100_GPG2_BASE,
-               .config = &gpio_cfg,
-               .chip   = {
-                       .base   = S5PC100_GPG2(0),
-                       .ngpio  = S5PC100_GPIO_G2_NR,
-                       .label  = "GPG2",
-               },
-       }, {
-               .base   = S5PC100_GPG3_BASE,
-               .config = &gpio_cfg,
-               .chip   = {
-                       .base   = S5PC100_GPG3(0),
-                       .ngpio  = S5PC100_GPIO_G3_NR,
-                       .label  = "GPG3",
-               },
-       }, {
-               .base   = S5PC100_GPH0_BASE,
-               .config = &gpio_cfg_eint,
-               .chip   = {
-                       .base   = S5PC100_GPH0(0),
-                       .ngpio  = S5PC100_GPIO_H0_NR,
-                       .label  = "GPH0",
-               },
-       }, {
-               .base   = S5PC100_GPH1_BASE,
-               .config = &gpio_cfg_eint,
-               .chip   = {
-                       .base   = S5PC100_GPH1(0),
-                       .ngpio  = S5PC100_GPIO_H1_NR,
-                       .label  = "GPH1",
-               },
-       }, {
-               .base   = S5PC100_GPH2_BASE,
-               .config = &gpio_cfg_eint,
-               .chip   = {
-                       .base   = S5PC100_GPH2(0),
-                       .ngpio  = S5PC100_GPIO_H2_NR,
-                       .label  = "GPH2",
-               },
-       }, {
-               .base   = S5PC100_GPH3_BASE,
-               .config = &gpio_cfg_eint,
-               .chip   = {
-                       .base   = S5PC100_GPH3(0),
-                       .ngpio  = S5PC100_GPIO_H3_NR,
-                       .label  = "GPH3",
-               },
-       }, {
-               .base   = S5PC100_GPI_BASE,
-               .config = &gpio_cfg,
-               .chip   = {
-                       .base   = S5PC100_GPI(0),
-                       .ngpio  = S5PC100_GPIO_I_NR,
-                       .label  = "GPI",
-               },
-       }, {
-               .base   = S5PC100_GPJ0_BASE,
-               .config = &gpio_cfg,
-               .chip   = {
-                       .base   = S5PC100_GPJ0(0),
-                       .ngpio  = S5PC100_GPIO_J0_NR,
-                       .label  = "GPJ0",
-               },
-       }, {
-               .base   = S5PC100_GPJ1_BASE,
-               .config = &gpio_cfg,
-               .chip   = {
-                       .base   = S5PC100_GPJ1(0),
-                       .ngpio  = S5PC100_GPIO_J1_NR,
-                       .label  = "GPJ1",
-               },
-       }, {
-               .base   = S5PC100_GPJ2_BASE,
-               .config = &gpio_cfg,
-               .chip   = {
-                       .base   = S5PC100_GPJ2(0),
-                       .ngpio  = S5PC100_GPIO_J2_NR,
-                       .label  = "GPJ2",
-               },
-       }, {
-               .base   = S5PC100_GPJ3_BASE,
-               .config = &gpio_cfg,
-               .chip   = {
-                       .base   = S5PC100_GPJ3(0),
-                       .ngpio  = S5PC100_GPIO_J3_NR,
-                       .label  = "GPJ3",
-               },
-       }, {
-               .base   = S5PC100_GPJ4_BASE,
-               .config = &gpio_cfg,
-               .chip   = {
-                       .base   = S5PC100_GPJ4(0),
-                       .ngpio  = S5PC100_GPIO_J4_NR,
-                       .label  = "GPJ4",
-               },
-       }, {
-               .base   = S5PC100_GPK0_BASE,
-               .config = &gpio_cfg_noint,
-               .chip   = {
-                       .base   = S5PC100_GPK0(0),
-                       .ngpio  = S5PC100_GPIO_K0_NR,
-                       .label  = "GPK0",
-               },
-       }, {
-               .base   = S5PC100_GPK1_BASE,
-               .config = &gpio_cfg_noint,
-               .chip   = {
-                       .base   = S5PC100_GPK1(0),
-                       .ngpio  = S5PC100_GPIO_K1_NR,
-                       .label  = "GPK1",
-               },
-       }, {
-               .base   = S5PC100_GPK2_BASE,
-               .config = &gpio_cfg_noint,
-               .chip   = {
-                       .base   = S5PC100_GPK2(0),
-                       .ngpio  = S5PC100_GPIO_K2_NR,
-                       .label  = "GPK2",
-               },
-       }, {
-               .base   = S5PC100_GPK3_BASE,
-               .config = &gpio_cfg_noint,
-               .chip   = {
-                       .base   = S5PC100_GPK3(0),
-                       .ngpio  = S5PC100_GPIO_K3_NR,
-                       .label  = "GPK3",
-               },
-       }, {
-               .base   = S5PC100_GPL0_BASE,
-               .config = &gpio_cfg_noint,
-               .chip   = {
-                       .base   = S5PC100_GPL0(0),
-                       .ngpio  = S5PC100_GPIO_L0_NR,
-                       .label  = "GPL0",
-               },
-       }, {
-               .base   = S5PC100_GPL1_BASE,
-               .config = &gpio_cfg_noint,
-               .chip   = {
-                       .base   = S5PC100_GPL1(0),
-                       .ngpio  = S5PC100_GPIO_L1_NR,
-                       .label  = "GPL1",
-               },
-       }, {
-               .base   = S5PC100_GPL2_BASE,
-               .config = &gpio_cfg_noint,
-               .chip   = {
-                       .base   = S5PC100_GPL2(0),
-                       .ngpio  = S5PC100_GPIO_L2_NR,
-                       .label  = "GPL2",
-               },
-       }, {
-               .base   = S5PC100_GPL3_BASE,
-               .config = &gpio_cfg_noint,
-               .chip   = {
-                       .base   = S5PC100_GPL3(0),
-                       .ngpio  = S5PC100_GPIO_L3_NR,
-                       .label  = "GPL3",
-               },
-       }, {
-               .base   = S5PC100_GPL4_BASE,
-               .config = &gpio_cfg_noint,
-               .chip   = {
-                       .base   = S5PC100_GPL4(0),
-                       .ngpio  = S5PC100_GPIO_L4_NR,
-                       .label  = "GPL4",
-               },
-       },
-};
-
-/* FIXME move from irq-gpio.c */
-extern struct irq_chip s5pc1xx_gpioint;
-extern void s5pc1xx_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc);
-
-static __init void s5pc100_gpiolib_link(struct s3c_gpio_chip *chip)
-{
-
-       /* Interrupt */
-       if (chip->config == &gpio_cfg) {
-               int i, irq;
-
-               chip->chip.to_irq = s5pc1xx_gpiolib_to_irq;
-
-               for (i = 0;  i < chip->chip.ngpio; i++) {
-                       irq = S3C_IRQ_GPIO_BASE + chip->chip.base + i;
-                       set_irq_chip(irq, &s5pc1xx_gpioint);
-                       set_irq_data(irq, &chip->chip);
-                       set_irq_handler(irq, handle_level_irq);
-                       set_irq_flags(irq, IRQF_VALID);
-               }
-       } else if (chip->config == &gpio_cfg_eint)
-               chip->chip.to_irq = s5pc1xx_gpiolib_to_eint;
-}
-
-static __init int s5pc1xx_gpiolib_init(void)
-{
-       struct s3c_gpio_chip *chip;
-       int nr_chips;
-
-       chip = s5pc100_gpio_chips;
-       nr_chips = ARRAY_SIZE(s5pc100_gpio_chips);
-
-       for (; nr_chips > 0; nr_chips--, chip++)
-               s5pc100_gpiolib_link(chip);
-
-       samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips,
-                                      ARRAY_SIZE(s5pc100_gpio_chips));
-       /* Interrupt */
-       set_irq_chained_handler(IRQ_GPIOINT, s5pc1xx_irq_gpioint_handler);
-
-       return 0;
-}
-core_initcall(s5pc1xx_gpiolib_init);
diff --git a/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h b/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h
deleted file mode 100644 (file)
index 43c7bc8..0000000
+++ /dev/null
@@ -1,70 +0,0 @@
-/* linux/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h
- *
- * Copyright 2009 Samsung Electronics Co.
- *      Byungho Min <bhmin@samsung.com>
- *
- * S5PC1XX - GPIO register definitions
- */
-
-#ifndef __ASM_PLAT_S5PC1XX_REGS_GPIO_H
-#define __ASM_PLAT_S5PC1XX_REGS_GPIO_H __FILE__
-
-#include <mach/map.h>
-
-/* S5PC100 */
-#define S5PC100_GPIO_BASE      S5PC1XX_VA_GPIO
-#define S5PC100_GPA0_BASE      (S5PC100_GPIO_BASE + 0x0000)
-#define S5PC100_GPA1_BASE      (S5PC100_GPIO_BASE + 0x0020)
-#define S5PC100_GPB_BASE       (S5PC100_GPIO_BASE + 0x0040)
-#define S5PC100_GPC_BASE       (S5PC100_GPIO_BASE + 0x0060)
-#define S5PC100_GPD_BASE       (S5PC100_GPIO_BASE + 0x0080)
-#define S5PC100_GPE0_BASE      (S5PC100_GPIO_BASE + 0x00A0)
-#define S5PC100_GPE1_BASE      (S5PC100_GPIO_BASE + 0x00C0)
-#define S5PC100_GPF0_BASE      (S5PC100_GPIO_BASE + 0x00E0)
-#define S5PC100_GPF1_BASE      (S5PC100_GPIO_BASE + 0x0100)
-#define S5PC100_GPF2_BASE      (S5PC100_GPIO_BASE + 0x0120)
-#define S5PC100_GPF3_BASE      (S5PC100_GPIO_BASE + 0x0140)
-#define S5PC100_GPG0_BASE      (S5PC100_GPIO_BASE + 0x0160)
-#define S5PC100_GPG1_BASE      (S5PC100_GPIO_BASE + 0x0180)
-#define S5PC100_GPG2_BASE      (S5PC100_GPIO_BASE + 0x01A0)
-#define S5PC100_GPG3_BASE      (S5PC100_GPIO_BASE + 0x01C0)
-#define S5PC100_GPH0_BASE      (S5PC100_GPIO_BASE + 0x0C00)
-#define S5PC100_GPH1_BASE      (S5PC100_GPIO_BASE + 0x0C20)
-#define S5PC100_GPH2_BASE      (S5PC100_GPIO_BASE + 0x0C40)
-#define S5PC100_GPH3_BASE      (S5PC100_GPIO_BASE + 0x0C60)
-#define S5PC100_GPI_BASE       (S5PC100_GPIO_BASE + 0x01E0)
-#define S5PC100_GPJ0_BASE      (S5PC100_GPIO_BASE + 0x0200)
-#define S5PC100_GPJ1_BASE      (S5PC100_GPIO_BASE + 0x0220)
-#define S5PC100_GPJ2_BASE      (S5PC100_GPIO_BASE + 0x0240)
-#define S5PC100_GPJ3_BASE      (S5PC100_GPIO_BASE + 0x0260)
-#define S5PC100_GPJ4_BASE      (S5PC100_GPIO_BASE + 0x0280)
-#define S5PC100_GPK0_BASE      (S5PC100_GPIO_BASE + 0x02A0)
-#define S5PC100_GPK1_BASE      (S5PC100_GPIO_BASE + 0x02C0)
-#define S5PC100_GPK2_BASE      (S5PC100_GPIO_BASE + 0x02E0)
-#define S5PC100_GPK3_BASE      (S5PC100_GPIO_BASE + 0x0300)
-#define S5PC100_GPL0_BASE      (S5PC100_GPIO_BASE + 0x0320)
-#define S5PC100_GPL1_BASE      (S5PC100_GPIO_BASE + 0x0340)
-#define S5PC100_GPL2_BASE      (S5PC100_GPIO_BASE + 0x0360)
-#define S5PC100_GPL3_BASE      (S5PC100_GPIO_BASE + 0x0380)
-#define S5PC100_GPL4_BASE      (S5PC100_GPIO_BASE + 0x03A0)
-#define S5PC100_EINT_BASE      (S5PC100_GPIO_BASE + 0x0E00)
-
-#define S5PC100_UHOST          (S5PC100_GPIO_BASE + 0x0B68)
-#define S5PC100_PDNEN          (S5PC100_GPIO_BASE + 0x0F80)
-
-/* PDNEN */
-#define S5PC100_PDNEN_CFG_PDNEN        (1 << 1)
-#define S5PC100_PDNEN_CFG_AUTO (0 << 1)
-#define S5PC100_PDNEN_POWERDOWN        (1 << 0)
-#define S5PC100_PDNEN_NORMAL   (0 << 0)
-
-/* Common part */
-/* External interrupt base is same at both s5pc100 and s5pc110 */
-#define S5PC1XX_EINT_BASE      (S5PC100_EINT_BASE)
-
-#define S5PC100_GPx_INPUT(__gpio)      (0x0 << ((__gpio) * 4))
-#define S5PC100_GPx_OUTPUT(__gpio)     (0x1 << ((__gpio) * 4))
-#define S5PC100_GPx_CONMASK(__gpio)    (0xf << ((__gpio) * 4))
-
-#endif /* __ASM_PLAT_S5PC1XX_REGS_GPIO_H */
-