drm/amd/display: Remove DISPCLK Limit Floor for Certain SMU Versions

[WHY]
SMU FW previously had an issue with lowering display clock to below 100
MHz, and a workaround was put in to limit it.  Newest SMU FW does not
have this issue, and no longer needs the 100MHz cap.

[HOW]
Remove the 100MHz cap based on the SMU FW version.

Signed-off-by: Sung Lee <sung.lee@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index 64cbd54..ab267dd 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -46,6 +46,7 @@
 /* Constants */
 
 #define LPDDR_MEM_RETRAIN_LATENCY 4.977 /* Number obtained from LPDDR4 Training Counter Requirement doc */
+#define SMU_VER_55_51_0 0x373300 /* SMU Version that is able to set DISPCLK below 100MHz */
 
 /* Macros */
 
@@ -720,6 +721,13 @@ void rn_clk_mgr_construct(
        } else {
                struct clk_log_info log_info = {0};
 
+               clk_mgr->smu_ver = rn_vbios_smu_get_smu_version(clk_mgr);
+
+               /* SMU Version 55.51.0 and up no longer have an issue
+                * that needs to limit minimum dispclk */
+               if (clk_mgr->smu_ver >= SMU_VER_55_51_0)
+                       debug->min_disp_clk_khz = 0;
+
                /* TODO: Check we get what we expect during bringup */
                clk_mgr->base.dentist_vco_freq_khz = get_vco_frequency_from_reg(clk_mgr);