riscv: Allow ptrace control of the tagged address ABI
authorSamuel Holland <samuel.holland@sifive.com>
Wed, 16 Oct 2024 20:27:47 +0000 (13:27 -0700)
committerPalmer Dabbelt <palmer@rivosinc.com>
Thu, 24 Oct 2024 21:12:57 +0000 (14:12 -0700)
This allows a tracer to control the ABI of the tracee, as on arm64.

Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Link: https://lore.kernel.org/r/20241016202814.4061541-7-samuel.holland@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
arch/riscv/kernel/ptrace.c
include/uapi/linux/elf.h

index 92731ff..ea67e9f 100644 (file)
@@ -28,6 +28,9 @@ enum riscv_regset {
 #ifdef CONFIG_RISCV_ISA_V
        REGSET_V,
 #endif
+#ifdef CONFIG_RISCV_ISA_SUPM
+       REGSET_TAGGED_ADDR_CTRL,
+#endif
 };
 
 static int riscv_gpr_get(struct task_struct *target,
@@ -152,6 +155,35 @@ static int riscv_vr_set(struct task_struct *target,
 }
 #endif
 
+#ifdef CONFIG_RISCV_ISA_SUPM
+static int tagged_addr_ctrl_get(struct task_struct *target,
+                               const struct user_regset *regset,
+                               struct membuf to)
+{
+       long ctrl = get_tagged_addr_ctrl(target);
+
+       if (IS_ERR_VALUE(ctrl))
+               return ctrl;
+
+       return membuf_write(&to, &ctrl, sizeof(ctrl));
+}
+
+static int tagged_addr_ctrl_set(struct task_struct *target,
+                               const struct user_regset *regset,
+                               unsigned int pos, unsigned int count,
+                               const void *kbuf, const void __user *ubuf)
+{
+       int ret;
+       long ctrl;
+
+       ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &ctrl, 0, -1);
+       if (ret)
+               return ret;
+
+       return set_tagged_addr_ctrl(target, ctrl);
+}
+#endif
+
 static const struct user_regset riscv_user_regset[] = {
        [REGSET_X] = {
                .core_note_type = NT_PRSTATUS,
@@ -182,6 +214,16 @@ static const struct user_regset riscv_user_regset[] = {
                .set = riscv_vr_set,
        },
 #endif
+#ifdef CONFIG_RISCV_ISA_SUPM
+       [REGSET_TAGGED_ADDR_CTRL] = {
+               .core_note_type = NT_RISCV_TAGGED_ADDR_CTRL,
+               .n = 1,
+               .size = sizeof(long),
+               .align = sizeof(long),
+               .regset_get = tagged_addr_ctrl_get,
+               .set = tagged_addr_ctrl_set,
+       },
+#endif
 };
 
 static const struct user_regset_view riscv_user_native_view = {
index b993598..a920cf8 100644 (file)
@@ -450,6 +450,7 @@ typedef struct elf64_shdr {
 #define NT_MIPS_MSA    0x802           /* MIPS SIMD registers */
 #define NT_RISCV_CSR   0x900           /* RISC-V Control and Status Registers */
 #define NT_RISCV_VECTOR        0x901           /* RISC-V vector registers */
+#define NT_RISCV_TAGGED_ADDR_CTRL 0x902        /* RISC-V tagged address control (prctl()) */
 #define NT_LOONGARCH_CPUCFG    0xa00   /* LoongArch CPU config registers */
 #define NT_LOONGARCH_CSR       0xa01   /* LoongArch control and status registers */
 #define NT_LOONGARCH_LSX       0xa02   /* LoongArch Loongson SIMD Extension registers */