drm/amdgpu: fix up GDS/GWS/OA shifting
authorChristian König <christian.koenig@amd.com>
Fri, 14 Sep 2018 14:06:31 +0000 (16:06 +0200)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 19 Sep 2018 17:38:48 +0000 (12:38 -0500)
That only worked by pure coincident. Completely remove the shifting and
always apply correct PAGE_SHIFT.

Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

index d762d78..8836186 100644 (file)
@@ -721,16 +721,16 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
                e->bo_va = amdgpu_vm_bo_find(vm, ttm_to_amdgpu_bo(e->tv.bo));
 
        if (gds) {
-               p->job->gds_base = amdgpu_bo_gpu_offset(gds);
-               p->job->gds_size = amdgpu_bo_size(gds);
+               p->job->gds_base = amdgpu_bo_gpu_offset(gds) >> PAGE_SHIFT;
+               p->job->gds_size = amdgpu_bo_size(gds) >> PAGE_SHIFT;
        }
        if (gws) {
-               p->job->gws_base = amdgpu_bo_gpu_offset(gws);
-               p->job->gws_size = amdgpu_bo_size(gws);
+               p->job->gws_base = amdgpu_bo_gpu_offset(gws) >> PAGE_SHIFT;
+               p->job->gws_size = amdgpu_bo_size(gws) >> PAGE_SHIFT;
        }
        if (oa) {
-               p->job->oa_base = amdgpu_bo_gpu_offset(oa);
-               p->job->oa_size = amdgpu_bo_size(oa);
+               p->job->oa_base = amdgpu_bo_gpu_offset(oa) >> PAGE_SHIFT;
+               p->job->oa_size = amdgpu_bo_size(oa) >> PAGE_SHIFT;
        }
 
        if (!r && p->uf_entry.tv.bo) {
index e73728d..ecbcefe 100644 (file)
 #ifndef __AMDGPU_GDS_H__
 #define __AMDGPU_GDS_H__
 
-/* Because TTM request that alloacted buffer should be PAGE_SIZE aligned,
- * we should report GDS/GWS/OA size as PAGE_SIZE aligned
- * */
-#define AMDGPU_GDS_SHIFT       2
-#define AMDGPU_GWS_SHIFT       PAGE_SHIFT
-#define AMDGPU_OA_SHIFT                PAGE_SHIFT
-
 struct amdgpu_ring;
 struct amdgpu_bo;
 
index d30a083..7b3d1eb 100644 (file)
@@ -244,16 +244,10 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
                        return -EINVAL;
                }
                flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
-               if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS)
-                       size = size << AMDGPU_GDS_SHIFT;
-               else if (args->in.domains == AMDGPU_GEM_DOMAIN_GWS)
-                       size = size << AMDGPU_GWS_SHIFT;
-               else if (args->in.domains == AMDGPU_GEM_DOMAIN_OA)
-                       size = size << AMDGPU_OA_SHIFT;
-               else
-                       return -EINVAL;
+               /* GDS allocations must be DW aligned */
+               if (args->in.domains & AMDGPU_GEM_DOMAIN_GDS)
+                       size = ALIGN(size, 4);
        }
-       size = roundup(size, PAGE_SIZE);
 
        if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
                r = amdgpu_bo_reserve(vm->root.base.bo, false);
index dc4b2f3..a64056d 100644 (file)
@@ -528,13 +528,13 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
                struct drm_amdgpu_info_gds gds_info;
 
                memset(&gds_info, 0, sizeof(gds_info));
-               gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size >> AMDGPU_GDS_SHIFT;
-               gds_info.compute_partition_size = adev->gds.mem.cs_partition_size >> AMDGPU_GDS_SHIFT;
-               gds_info.gds_total_size = adev->gds.mem.total_size >> AMDGPU_GDS_SHIFT;
-               gds_info.gws_per_gfx_partition = adev->gds.gws.gfx_partition_size >> AMDGPU_GWS_SHIFT;
-               gds_info.gws_per_compute_partition = adev->gds.gws.cs_partition_size >> AMDGPU_GWS_SHIFT;
-               gds_info.oa_per_gfx_partition = adev->gds.oa.gfx_partition_size >> AMDGPU_OA_SHIFT;
-               gds_info.oa_per_compute_partition = adev->gds.oa.cs_partition_size >> AMDGPU_OA_SHIFT;
+               gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size;
+               gds_info.compute_partition_size = adev->gds.mem.cs_partition_size;
+               gds_info.gds_total_size = adev->gds.mem.total_size;
+               gds_info.gws_per_gfx_partition = adev->gds.gws.gfx_partition_size;
+               gds_info.gws_per_compute_partition = adev->gds.gws.cs_partition_size;
+               gds_info.oa_per_gfx_partition = adev->gds.oa.gfx_partition_size;
+               gds_info.oa_per_compute_partition = adev->gds.oa.cs_partition_size;
                return copy_to_user(out, &gds_info,
                                    min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
        }
index 113738c..904014d 100644 (file)
@@ -427,7 +427,11 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev,
        int r;
 
        page_align = roundup(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT;
-       size = ALIGN(size, PAGE_SIZE);
+       if (bp->domain & (AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS |
+                         AMDGPU_GEM_DOMAIN_OA))
+               size <<= PAGE_SHIFT;
+       else
+               size = ALIGN(size, PAGE_SIZE);
 
        if (!amdgpu_bo_validate_size(adev, size, bp->domain))
                return -ENOMEM;
index d619108..0c4ab72 100644 (file)
@@ -1845,19 +1845,10 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
                 (unsigned)(gtt_size / (1024 * 1024)));
 
        /* Initialize various on-chip memory pools */
-       adev->gds.mem.total_size = adev->gds.mem.total_size << AMDGPU_GDS_SHIFT;
-       adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size << AMDGPU_GDS_SHIFT;
-       adev->gds.mem.cs_partition_size = adev->gds.mem.cs_partition_size << AMDGPU_GDS_SHIFT;
-       adev->gds.gws.total_size = adev->gds.gws.total_size << AMDGPU_GWS_SHIFT;
-       adev->gds.gws.gfx_partition_size = adev->gds.gws.gfx_partition_size << AMDGPU_GWS_SHIFT;
-       adev->gds.gws.cs_partition_size = adev->gds.gws.cs_partition_size << AMDGPU_GWS_SHIFT;
-       adev->gds.oa.total_size = adev->gds.oa.total_size << AMDGPU_OA_SHIFT;
-       adev->gds.oa.gfx_partition_size = adev->gds.oa.gfx_partition_size << AMDGPU_OA_SHIFT;
-       adev->gds.oa.cs_partition_size = adev->gds.oa.cs_partition_size << AMDGPU_OA_SHIFT;
        /* GDS Memory */
        if (adev->gds.mem.total_size) {
                r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
-                                  adev->gds.mem.total_size >> PAGE_SHIFT);
+                                  adev->gds.mem.total_size);
                if (r) {
                        DRM_ERROR("Failed initializing GDS heap.\n");
                        return r;
@@ -1867,7 +1858,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
        /* GWS */
        if (adev->gds.gws.total_size) {
                r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
-                                  adev->gds.gws.total_size >> PAGE_SHIFT);
+                                  adev->gds.gws.total_size);
                if (r) {
                        DRM_ERROR("Failed initializing gws heap.\n");
                        return r;
@@ -1877,7 +1868,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
        /* OA */
        if (adev->gds.oa.total_size) {
                r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
-                                  adev->gds.oa.total_size >> PAGE_SHIFT);
+                                  adev->gds.oa.total_size);
                if (r) {
                        DRM_ERROR("Failed initializing oa heap.\n");
                        return r;
index a15d9c0..c0f9732 100644 (file)
@@ -4170,15 +4170,6 @@ static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
                                          uint32_t gws_base, uint32_t gws_size,
                                          uint32_t oa_base, uint32_t oa_size)
 {
-       gds_base = gds_base >> AMDGPU_GDS_SHIFT;
-       gds_size = gds_size >> AMDGPU_GDS_SHIFT;
-
-       gws_base = gws_base >> AMDGPU_GWS_SHIFT;
-       gws_size = gws_size >> AMDGPU_GWS_SHIFT;
-
-       oa_base = oa_base >> AMDGPU_OA_SHIFT;
-       oa_size = oa_size >> AMDGPU_OA_SHIFT;
-
        /* GDS Base */
        amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
        amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
index 11e6ccd..96df23c 100644 (file)
@@ -5396,15 +5396,6 @@ static void gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
                                          uint32_t gws_base, uint32_t gws_size,
                                          uint32_t oa_base, uint32_t oa_size)
 {
-       gds_base = gds_base >> AMDGPU_GDS_SHIFT;
-       gds_size = gds_size >> AMDGPU_GDS_SHIFT;
-
-       gws_base = gws_base >> AMDGPU_GWS_SHIFT;
-       gws_size = gws_size >> AMDGPU_GWS_SHIFT;
-
-       oa_base = oa_base >> AMDGPU_OA_SHIFT;
-       oa_size = oa_size >> AMDGPU_OA_SHIFT;
-
        /* GDS Base */
        amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
        amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
index 1a298f1..528a8a5 100644 (file)
@@ -1527,8 +1527,7 @@ static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)
        gfx_v9_0_write_data_to_reg(ring, 0, false,
                                   SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
                                   (adev->gds.mem.total_size +
-                                   adev->gfx.ngg.gds_reserve_size) >>
-                                  AMDGPU_GDS_SHIFT);
+                                   adev->gfx.ngg.gds_reserve_size));
 
        amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
        amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
@@ -3472,15 +3471,6 @@ static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
 {
        struct amdgpu_device *adev = ring->adev;
 
-       gds_base = gds_base >> AMDGPU_GDS_SHIFT;
-       gds_size = gds_size >> AMDGPU_GDS_SHIFT;
-
-       gws_base = gws_base >> AMDGPU_GWS_SHIFT;
-       gws_size = gws_size >> AMDGPU_GWS_SHIFT;
-
-       oa_base = oa_base >> AMDGPU_OA_SHIFT;
-       oa_size = oa_size >> AMDGPU_OA_SHIFT;
-
        /* GDS Base */
        gfx_v9_0_write_data_to_reg(ring, 0, false,
                                   SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,