drm/amd/display: fix an error check condition for synced pipes
authorAurabindo Pillai <aurabindo.pillai@amd.com>
Thu, 15 Dec 2022 22:07:55 +0000 (17:07 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 17 Jan 2023 20:39:33 +0000 (15:39 -0500)
Checking for disabled master pipe on a timing synchronized pipe is
incorrect in the case of ODM combine. This case is acceptable as long as
the disabled master pipe is part of the ODM tree. Skip printing error
message if this condition holds true.

Tested-by: Daniel Wheeler <Daniel.Wheeler@amd.com>
Reviewed-by: Dillon Varone <Dillon.Varone@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/core/dc_resource.c

index 91d56a3..a5b5f85 100644 (file)
@@ -3821,9 +3821,20 @@ void check_syncd_pipes_for_disabled_master_pipe(struct dc *dc,
                pipe_ctx_check = &context->res_ctx.pipe_ctx[i];
 
                if ((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx_check) == disabled_master_pipe_idx) &&
-                       IS_PIPE_SYNCD_VALID(pipe_ctx_check) && (i != disabled_master_pipe_idx))
+                   IS_PIPE_SYNCD_VALID(pipe_ctx_check) && (i != disabled_master_pipe_idx)) {
+                       struct pipe_ctx *first_pipe = pipe_ctx_check;
+
+                       while (first_pipe->prev_odm_pipe)
+                               first_pipe = first_pipe->prev_odm_pipe;
+                       /* When ODM combine is enabled, this case is expected. If the disabled pipe
+                        * is part of the ODM tree, then we should not print an error.
+                        * */
+                       if (first_pipe->pipe_idx == disabled_master_pipe_idx)
+                               continue;
+
                        DC_ERR("DC: Failure: pipe_idx[%d] syncd with disabled master pipe_idx[%d]\n",
-                               i, disabled_master_pipe_idx);
+                                  i, disabled_master_pipe_idx);
+               }
        }
 }