clk: renesas: r9a08g045: Add IA55 pclk and its reset

An IA55 interrupt controller is available on the RZ/G3S SoC.  Add the
IA55 pclk and its reset.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20231120111820.87398-2-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c
index 4394cb2..ea3beca 100644 (file)
--- a/drivers/clk/renesas/r9a08g045-cpg.c
+++ b/drivers/clk/renesas/r9a08g045-cpg.c
@@ -188,6 +188,7 @@ static const struct cpg_core_clk r9a08g045_core_clks[] __initconst = {
 
 static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {
        DEF_MOD("gic_gicclk",           R9A08G045_GIC600_GICCLK, R9A08G045_CLK_P1, 0x514, 0),
+       DEF_MOD("ia55_pclk",            R9A08G045_IA55_PCLK, R9A08G045_CLK_P2, 0x518, 0),
        DEF_MOD("ia55_clk",             R9A08G045_IA55_CLK, R9A08G045_CLK_P1, 0x518, 1),
        DEF_MOD("dmac_aclk",            R9A08G045_DMAC_ACLK, R9A08G045_CLK_P3, 0x52c, 0),
        DEF_MOD("sdhi0_imclk",          R9A08G045_SDHI0_IMCLK, CLK_SD0_DIV4, 0x554, 0),
@@ -209,6 +210,7 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {
 static const struct rzg2l_reset r9a08g045_resets[] = {
        DEF_RST(R9A08G045_GIC600_GICRESET_N, 0x814, 0),
        DEF_RST(R9A08G045_GIC600_DBG_GICRESET_N, 0x814, 1),
+       DEF_RST(R9A08G045_IA55_RESETN, 0x818, 0),
        DEF_RST(R9A08G045_SDHI0_IXRST, 0x854, 0),
        DEF_RST(R9A08G045_SDHI1_IXRST, 0x854, 1),
        DEF_RST(R9A08G045_SDHI2_IXRST, 0x854, 2),
@@ -220,6 +222,7 @@ static const struct rzg2l_reset r9a08g045_resets[] = {
 
 static const unsigned int r9a08g045_crit_mod_clks[] __initconst = {
        MOD_CLK_BASE + R9A08G045_GIC600_GICCLK,
+       MOD_CLK_BASE + R9A08G045_IA55_PCLK,
        MOD_CLK_BASE + R9A08G045_IA55_CLK,
        MOD_CLK_BASE + R9A08G045_DMAC_ACLK,
 };