ARM: tegra: Add CPU thermal zones to Nyan device-tree

CPU of Nyan Chromebooks is overheating badly because apparently hardware
soctherm controller doesn't work well. Add CPU thermal zones to enable
software thermal control over CPU and fix the overheat trouble.

Tested-by: Thomas Graichen <thomas.graichen@gmail.com> # T124 Nyan Big
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi
index f693daa..a93cfb4 100644 (file)
--- a/arch/arm/boot/dts/tegra124-nyan.dtsi
+++ b/arch/arm/boot/dts/tegra124-nyan.dtsi
@@ -1,5 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/thermal/thermal.h>
 #include "tegra124.dtsi"
 
 / {
@@ -87,7 +88,7 @@
                        interrupts = <TEGRA_GPIO(H, 4) IRQ_TYPE_EDGE_FALLING>;
                };
 
-               temperature-sensor@4c {
+               tmp451: temperature-sensor@4c {
                        compatible = "ti,tmp451";
                        reg = <0x4c>;
                        interrupt-parent = <&gpio>;
@@ -789,6 +790,52 @@
                gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
                priority = <200>;
        };
+
+       cpus {
+               cpu0: cpu@0 {
+                       #cooling-cells = <2>;
+               };
+
+               cpu1: cpu@1 {
+                       #cooling-cells = <2>;
+               };
+
+               cpu2: cpu@2 {
+                       #cooling-cells = <2>;
+               };
+
+               cpu3: cpu@3 {
+                       #cooling-cells = <2>;
+               };
+       };
+
+       thermal-zones {
+               cpu-skin-thermal {
+                       polling-delay-passive = <1000>; /* milliseconds */
+                       polling-delay = <5000>; /* milliseconds */
+
+                       thermal-sensors = <&tmp451 0>;
+
+                       trips {
+                               cpu_passive_trip: cpu-alert0 {
+                                       /* throttle at 70C until temperature drops to 69.8C */
+                                       temperature = <70000>;
+                                       hysteresis = <200>;
+                                       type = "passive";
+                               };
+                       };
+
+                       cooling-maps {
+                               map0 {
+                                       trip = <&cpu_passive_trip>;
+                                       cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                        <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                        <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                        <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                               };
+                       };
+               };
+       };
 };
 
 #include "cros-ec-keyboard.dtsi"