wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
mutex_lock(&fbc->lock);
- if (intel_fbc_is_active(dev_priv))
+ if (intel_fbc_is_active(dev_priv)) {
seq_puts(m, "FBC enabled\n");
- else
+ seq_printf(m, "Compressing: %s\n",
+ yesno(intel_fbc_is_compressing(dev_priv)));
+ } else {
seq_printf(m, "FBC disabled: %s\n", fbc->no_fbc_reason);
-
- if (intel_fbc_is_active(dev_priv)) {
- u32 mask;
-
- if (DISPLAY_VER(dev_priv) >= 8)
- mask = intel_de_read(dev_priv, IVB_FBC_STATUS2) & BDW_FBC_COMP_SEG_MASK;
- else if (DISPLAY_VER(dev_priv) >= 7)
- mask = intel_de_read(dev_priv, IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK;
- else if (DISPLAY_VER(dev_priv) >= 5)
- mask = intel_de_read(dev_priv, ILK_DPFC_STATUS) & ILK_DPFC_COMP_SEG_MASK;
- else if (IS_G4X(dev_priv))
- mask = intel_de_read(dev_priv, DPFC_STATUS) & DPFC_COMP_SEG_MASK;
- else
- mask = intel_de_read(dev_priv, FBC_STATUS) &
- (FBC_STAT_COMPRESSING | FBC_STAT_COMPRESSED);
-
- seq_printf(m, "Compressing: %s\n", yesno(mask));
}
mutex_unlock(&fbc->lock);
return intel_de_read(dev_priv, FBC_CONTROL) & FBC_CTL_EN;
}
+static bool i8xx_fbc_is_compressing(struct drm_i915_private *i915)
+{
+ return intel_de_read(i915, FBC_STATUS) &
+ (FBC_STAT_COMPRESSING | FBC_STAT_COMPRESSED);
+}
+
static u32 g4x_dpfc_ctl_limit(struct drm_i915_private *i915)
{
switch (i915->fbc.limit) {
return intel_de_read(dev_priv, DPFC_CONTROL) & DPFC_CTL_EN;
}
+static bool g4x_fbc_is_compressing(struct drm_i915_private *i915)
+{
+ return intel_de_read(i915, DPFC_STATUS) & DPFC_COMP_SEG_MASK;
+}
+
static void i8xx_fbc_recompress(struct drm_i915_private *dev_priv)
{
struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
return intel_de_read(dev_priv, ILK_DPFC_CONTROL) & DPFC_CTL_EN;
}
+static bool ilk_fbc_is_compressing(struct drm_i915_private *i915)
+{
+ return intel_de_read(i915, ILK_DPFC_STATUS) & ILK_DPFC_COMP_SEG_MASK;
+}
+
static void glk_fbc_program_cfb_stride(struct drm_i915_private *i915)
{
struct intel_fbc *fbc = &i915->fbc;
intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
}
+static bool gen7_fbc_is_compressing(struct drm_i915_private *i915)
+{
+ if (DISPLAY_VER(i915) >= 8)
+ return intel_de_read(i915, IVB_FBC_STATUS2) & BDW_FBC_COMP_SEG_MASK;
+ else
+ return intel_de_read(i915, IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK;
+}
+
static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv)
{
if (DISPLAY_VER(dev_priv) >= 5)
i8xx_fbc_deactivate(dev_priv);
}
+bool intel_fbc_is_compressing(struct drm_i915_private *i915)
+{
+ if (DISPLAY_VER(i915) >= 7)
+ return gen7_fbc_is_compressing(i915);
+ else if (DISPLAY_VER(i915) >= 5)
+ return ilk_fbc_is_compressing(i915);
+ else if (IS_G4X(i915))
+ return g4x_fbc_is_compressing(i915);
+ else
+ return i8xx_fbc_is_compressing(i915);
+}
+
/**
* intel_fbc_is_active - Is FBC active?
* @dev_priv: i915 device instance
void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
struct intel_atomic_state *state);
bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
+bool intel_fbc_is_compressing(struct drm_i915_private *dev_priv);
bool intel_fbc_pre_update(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void intel_fbc_post_update(struct intel_atomic_state *state,