riscv: hwprobe: export Zhintntl ISA extension
authorClément Léger <cleger@rivosinc.com>
Tue, 14 Nov 2023 14:12:49 +0000 (09:12 -0500)
committerPalmer Dabbelt <palmer@rivosinc.com>
Tue, 12 Dec 2023 23:45:10 +0000 (15:45 -0800)
Export Zihintntl extension[1] through hwprobe.

Link: https://drive.google.com/file/d/13_wsN8YmRfH8YWysFyTX-DjTkCnBd9hj/view
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Evan Green <evan@rivosinc.com>
Link: https://lore.kernel.org/r/20231114141256.126749-14-cleger@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Documentation/arch/riscv/hwprobe.rst
arch/riscv/include/uapi/asm/hwprobe.h
arch/riscv/kernel/sys_riscv.c

index 397d531..aa8ebee 100644 (file)
@@ -146,6 +146,9 @@ The following keys are defined:
   * :c:macro:`RISCV_HWPROBE_EXT_ZFHMIN`: The Zfhmin extension version 1.0 is
        supported as defined in the RISC-V ISA manual.
 
+  * :c:macro:`RISCV_HWPROBE_EXT_ZIHINTNTL`: The Zihintntl extension version 1.0
+       is supported as defined in the RISC-V ISA manual.
+
 * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
   information about the selected set of processors.
 
index 2d96077..d72c69e 100644 (file)
@@ -52,6 +52,7 @@ struct riscv_hwprobe {
 #define                RISCV_HWPROBE_EXT_ZVKT          (1 << 26)
 #define                RISCV_HWPROBE_EXT_ZFH           (1 << 27)
 #define                RISCV_HWPROBE_EXT_ZFHMIN        (1 << 28)
+#define                RISCV_HWPROBE_EXT_ZIHINTNTL     (1 << 29)
 #define RISCV_HWPROBE_KEY_CPUPERF_0    5
 #define                RISCV_HWPROBE_MISALIGNED_UNKNOWN        (0 << 0)
 #define                RISCV_HWPROBE_MISALIGNED_EMULATED       (1 << 0)
index d776c6c..a46e4f6 100644 (file)
@@ -173,6 +173,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
                EXT_KEY(ZKSED);
                EXT_KEY(ZKSH);
                EXT_KEY(ZKT);
+               EXT_KEY(ZIHINTNTL);
 
                if (has_vector()) {
                        EXT_KEY(ZVBB);