net/mlx5e: TX, Inline function mlx5e_tls_handle_tx_wqe()
authorTariq Toukan <tariqt@nvidia.com>
Tue, 16 Feb 2021 10:27:57 +0000 (12:27 +0200)
committerSaeed Mahameed <saeedm@nvidia.com>
Fri, 16 Apr 2021 18:48:05 +0000 (11:48 -0700)
When TLS is supported, WQE ctrl segment of every transmitted packet
is updated with the (possibly empty, for non-TLS packets) TISN field.

Take this one-liner function into the header file and inline it,
to save the overhead of a function call per packet.

While here, remove unused function parameter.

Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
drivers/net/ethernet/mellanox/mlx5/core/en_accel/en_accel.h
drivers/net/ethernet/mellanox/mlx5/core/en_accel/tls_rxtx.c
drivers/net/ethernet/mellanox/mlx5/core/en_accel/tls_rxtx.h

index 043c86c..00af0b8 100644 (file)
@@ -185,7 +185,7 @@ static inline void mlx5e_accel_tx_finish(struct mlx5e_txqsq *sq,
                                         struct mlx5_wqe_inline_seg *inlseg)
 {
 #ifdef CONFIG_MLX5_EN_TLS
-       mlx5e_tls_handle_tx_wqe(sq, &wqe->ctrl, &state->tls);
+       mlx5e_tls_handle_tx_wqe(&wqe->ctrl, &state->tls);
 #endif
 
 #ifdef CONFIG_MLX5_EN_IPSEC
index 97cbea7..82dc09a 100644 (file)
@@ -298,12 +298,6 @@ err_out:
        return false;
 }
 
-void mlx5e_tls_handle_tx_wqe(struct mlx5e_txqsq *sq, struct mlx5_wqe_ctrl_seg *cseg,
-                            struct mlx5e_accel_tx_tls_state *state)
-{
-       cseg->tis_tir_num = cpu_to_be32(state->tls_tisn << 8);
-}
-
 static int tls_update_resync_sn(struct net_device *netdev,
                                struct sk_buff *skb,
                                struct mlx5e_tls_metadata *mdata)
index 5c34432..0ca0a02 100644 (file)
@@ -53,8 +53,12 @@ static inline bool mlx5e_tls_skb_offloaded(struct sk_buff *skb)
        return skb->sk && tls_is_sk_tx_device_offloaded(skb->sk);
 }
 
-void mlx5e_tls_handle_tx_wqe(struct mlx5e_txqsq *sq, struct mlx5_wqe_ctrl_seg *cseg,
-                            struct mlx5e_accel_tx_tls_state *state);
+static inline void
+mlx5e_tls_handle_tx_wqe(struct mlx5_wqe_ctrl_seg *cseg,
+                       struct mlx5e_accel_tx_tls_state *state)
+{
+       cseg->tis_tir_num = cpu_to_be32(state->tls_tisn << 8);
+}
 
 void mlx5e_tls_handle_rx_skb_metadata(struct mlx5e_rq *rq, struct sk_buff *skb,
                                      u32 *cqe_bcnt);