drm/xe/gt_clock: Convert register access to use xe_mmio

Stop using GT pointers for register access.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240910234719.3335472-79-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/xe/xe_gt_clock.c b/drivers/gpu/drm/xe/xe_gt_clock.c
index 86c2d62..cc2ae15 100644 (file)
--- a/drivers/gpu/drm/xe/xe_gt_clock.c
+++ b/drivers/gpu/drm/xe/xe_gt_clock.c
@@ -17,7 +17,7 @@
 
 static u32 read_reference_ts_freq(struct xe_gt *gt)
 {
-       u32 ts_override = xe_mmio_read32(gt, TIMESTAMP_OVERRIDE);
+       u32 ts_override = xe_mmio_read32(&gt->mmio, TIMESTAMP_OVERRIDE);
        u32 base_freq, frac_freq;
 
        base_freq = REG_FIELD_GET(TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK,
@@ -57,7 +57,7 @@ static u32 get_crystal_clock_freq(u32 rpm_config_reg)
 
 int xe_gt_clock_init(struct xe_gt *gt)
 {
-       u32 ctc_reg = xe_mmio_read32(gt, CTC_MODE);
+       u32 ctc_reg = xe_mmio_read32(&gt->mmio, CTC_MODE);
        u32 freq = 0;
 
        /* Assuming gen11+ so assert this assumption is correct */
@@ -66,7 +66,7 @@ int xe_gt_clock_init(struct xe_gt *gt)
        if (ctc_reg & CTC_SOURCE_DIVIDE_LOGIC) {
                freq = read_reference_ts_freq(gt);
        } else {
-               u32 c0 = xe_mmio_read32(gt, RPM_CONFIG0);
+               u32 c0 = xe_mmio_read32(&gt->mmio, RPM_CONFIG0);
 
                freq = get_crystal_clock_freq(c0);