drm/amd/display: Revert "drm/amd/display: remove duplicated edp relink to fastboot"

Revert commit 984abb5384b0 ("drm/amd/display: remove duplicated edp relink to fastboot")

Because it cause 4k EDP not light up on boot

Reviewed-by: Tom Chung <chiahsuan.chung@amd.com>
Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 2436a29..8c865c9 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1215,6 +1215,64 @@ static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
        dc_release_state(current_ctx);
 }
 
+static void disable_vbios_mode_if_required(
+               struct dc *dc,
+               struct dc_state *context)
+{
+       unsigned int i, j;
+
+       /* check if timing_changed, disable stream*/
+       for (i = 0; i < dc->res_pool->pipe_count; i++) {
+               struct dc_stream_state *stream = NULL;
+               struct dc_link *link = NULL;
+               struct pipe_ctx *pipe = NULL;
+
+               pipe = &context->res_ctx.pipe_ctx[i];
+               stream = pipe->stream;
+               if (stream == NULL)
+                       continue;
+
+               // only looking for first odm pipe
+               if (pipe->prev_odm_pipe)
+                       continue;
+
+               if (stream->link->local_sink &&
+                       stream->link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
+                       link = stream->link;
+               }
+
+               if (link != NULL && link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
+                       unsigned int enc_inst, tg_inst = 0;
+                       unsigned int pix_clk_100hz;
+
+                       enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
+                       if (enc_inst != ENGINE_ID_UNKNOWN) {
+                               for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
+                                       if (dc->res_pool->stream_enc[j]->id == enc_inst) {
+                                               tg_inst = dc->res_pool->stream_enc[j]->funcs->dig_source_otg(
+                                                       dc->res_pool->stream_enc[j]);
+                                               break;
+                                       }
+                               }
+
+                               dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
+                                       dc->res_pool->dp_clock_source,
+                                       tg_inst, &pix_clk_100hz);
+
+                               if (link->link_status.link_active) {
+                                       uint32_t requested_pix_clk_100hz =
+                                               pipe->stream_res.pix_clk_params.requested_pix_clk_100hz;
+
+                                       if (pix_clk_100hz != requested_pix_clk_100hz) {
+                                               dc->link_srv->set_dpms_off(pipe);
+                                               pipe->stream->dpms_off = false;
+                                       }
+                               }
+                       }
+               }
+       }
+}
+
 static void wait_for_no_pipes_pending(struct dc *dc, struct dc_state *context)
 {
        int i;
@@ -1784,6 +1842,7 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
                dc_streams[i] =  context->streams[i];
 
        if (!dcb->funcs->is_accelerated_mode(dcb)) {
+               disable_vbios_mode_if_required(dc, context);
                dc->hwss.enable_accelerated_mode(dc, context);
        }