drm/amd/display: Temporarily disable HPO PG on DCN35

[WHY]
On hotpluggin a 4k144 HDMI FRL setup, display fails FRL link training
and falls back to TMDS which is caused by driver not ungating HPO before
doing FRL link training.

[HOW]
Enable debug flag to disable HPO power gate in DCN35

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Nicholas Susanto <nicholas.susanto@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
index 0094ef2..67ab8c1 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
@@ -721,7 +721,7 @@ static const struct dc_debug_options debug_defaults_drv = {
        .disable_dpp_power_gate = true,
        .disable_hubp_power_gate = true,
        .disable_optc_power_gate = true, /*should the same as above two*/
-       .disable_hpo_power_gate = false, /*dmubfw force domain25 on*/
+       .disable_hpo_power_gate = true, /*dmubfw force domain25 on*/
        .disable_clock_gate = false,
        .disable_dsc_power_gate = true,
        .vsr_support = true,