net/mlx5: Expose bits for enabling out-of-order by default

Add needed HW bits for enabling out-of-order by default and
use go_back_n when out-of-order is not needed.

Signed-off-by: Or Har-Toov <ohartoov@nvidia.com>
Signed-off-by: Leon Romanovsky <leonro@nvidia.com>
Link: https://lore.kernel.org/r/75d6dfe263989a05c08c43406132b336ea12d00a.1679230449.git.leon@kernel.org
Signed-off-by: Leon Romanovsky <leon@kernel.org>

diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index 66d76e9..62039b1 100644 (file)
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -1077,7 +1077,9 @@ struct mlx5_ifc_roce_cap_bits {
        u8         sw_r_roce_src_udp_port[0x1];
        u8         fl_rc_qp_when_roce_disabled[0x1];
        u8         fl_rc_qp_when_roce_enabled[0x1];
-       u8         reserved_at_7[0x17];
+       u8         reserved_at_7[0x1];
+       u8         qp_ooo_transmit_default[0x1];
+       u8         reserved_at_9[0x15];
        u8         qp_ts_format[0x2];
 
        u8         reserved_at_20[0x60];
@@ -1493,7 +1495,8 @@ struct mlx5_ifc_cmd_hca_cap_bits {
        u8         reserved_at_b0[0x1];
        u8         uplink_follow[0x1];
        u8         ts_cqe_to_dest_cqn[0x1];
-       u8         reserved_at_b3[0x7];
+       u8         reserved_at_b3[0x6];
+       u8         go_back_n[0x1];
        u8         shampo[0x1];
        u8         reserved_at_bb[0x5];
 
@@ -3261,7 +3264,8 @@ struct mlx5_ifc_qpc_bits {
        u8         log_rq_stride[0x3];
        u8         no_sq[0x1];
        u8         log_sq_size[0x4];
-       u8         reserved_at_55[0x3];
+       u8         reserved_at_55[0x1];
+       u8         retry_mode[0x2];
        u8         ts_format[0x2];
        u8         reserved_at_5a[0x1];
        u8         rlky[0x1];